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RISC-V: Add EM_RISCV to kexec UAPI header
Add RISC-V to the list of supported kexec architectures, we need to add the definition early-on so that later patches can use it. EM_RISCV is 243 as per ELF psABI specification here: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md Signed-off-by: Nick Kossifidis <mick@ics.forth.gr> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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@ -42,6 +42,7 @@
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#define KEXEC_ARCH_MIPS_LE (10 << 16)
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#define KEXEC_ARCH_MIPS ( 8 << 16)
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#define KEXEC_ARCH_AARCH64 (183 << 16)
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#define KEXEC_ARCH_RISCV (243 << 16)
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/* The artificial cap on the number of segments passed to kexec_load. */
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#define KEXEC_SEGMENT_MAX 16
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