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pinctrl: renesas: r8a77470: Share QSPI pin group data
Pin groups qspi[01]_data2 are subsets of qspi[01]_data4. This reduces kernel size by 32 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/2d877878bda39109a1a5caf5c01c798c771d3fda.1640269757.git.geert+renesas@glider.be
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1 changed files with 8 additions and 22 deletions
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@ -1623,19 +1623,12 @@ static const unsigned int qspi0_ctrl_pins[] = {
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static const unsigned int qspi0_ctrl_mux[] = {
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static const unsigned int qspi0_ctrl_mux[] = {
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QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
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};
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};
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static const unsigned int qspi0_data2_pins[] = {
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static const unsigned int qspi0_data_pins[] = {
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/* MOSI_IO0, MISO_IO1 */
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RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
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};
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static const unsigned int qspi0_data2_mux[] = {
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QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
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};
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static const unsigned int qspi0_data4_pins[] = {
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
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RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
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RCAR_GP_PIN(1, 20),
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RCAR_GP_PIN(1, 20),
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};
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};
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static const unsigned int qspi0_data4_mux[] = {
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static const unsigned int qspi0_data_mux[] = {
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QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
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QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
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QSPI0_IO2_MARK, QSPI0_IO3_MARK,
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QSPI0_IO2_MARK, QSPI0_IO3_MARK,
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};
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};
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@ -1646,19 +1639,12 @@ static const unsigned int qspi1_ctrl_pins[] = {
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static const unsigned int qspi1_ctrl_mux[] = {
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static const unsigned int qspi1_ctrl_mux[] = {
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QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
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};
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};
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static const unsigned int qspi1_data2_pins[] = {
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static const unsigned int qspi1_data_pins[] = {
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/* MOSI_IO0, MISO_IO1 */
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RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
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};
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static const unsigned int qspi1_data2_mux[] = {
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QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
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};
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static const unsigned int qspi1_data4_pins[] = {
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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/* MOSI_IO0, MISO_IO1, IO2, IO3 */
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RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
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RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
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RCAR_GP_PIN(4, 8),
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RCAR_GP_PIN(4, 8),
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};
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};
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static const unsigned int qspi1_data4_mux[] = {
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static const unsigned int qspi1_data_mux[] = {
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QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
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QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
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QSPI1_IO2_MARK, QSPI1_IO3_MARK,
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QSPI1_IO2_MARK, QSPI1_IO3_MARK,
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};
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};
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@ -2201,11 +2187,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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BUS_DATA_PIN_GROUP(mmc_data, 8),
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BUS_DATA_PIN_GROUP(mmc_data, 8),
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SH_PFC_PIN_GROUP(mmc_ctrl),
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SH_PFC_PIN_GROUP(mmc_ctrl),
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SH_PFC_PIN_GROUP(qspi0_ctrl),
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SH_PFC_PIN_GROUP(qspi0_ctrl),
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SH_PFC_PIN_GROUP(qspi0_data2),
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BUS_DATA_PIN_GROUP(qspi0_data, 2),
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SH_PFC_PIN_GROUP(qspi0_data4),
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BUS_DATA_PIN_GROUP(qspi0_data, 4),
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SH_PFC_PIN_GROUP(qspi1_ctrl),
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SH_PFC_PIN_GROUP(qspi1_ctrl),
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SH_PFC_PIN_GROUP(qspi1_data2),
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BUS_DATA_PIN_GROUP(qspi1_data, 2),
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SH_PFC_PIN_GROUP(qspi1_data4),
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BUS_DATA_PIN_GROUP(qspi1_data, 4),
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SH_PFC_PIN_GROUP(scif0_data_a),
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SH_PFC_PIN_GROUP(scif0_data_a),
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SH_PFC_PIN_GROUP(scif0_data_b),
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SH_PFC_PIN_GROUP(scif0_data_b),
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SH_PFC_PIN_GROUP(scif0_data_c),
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SH_PFC_PIN_GROUP(scif0_data_c),
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