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PCI: designware: Wait for iATU enable
Add a loop with timeout to make sure the iATU is really enabled before subsequent config and I/O accesses. [bhelgaas: split to separate patch, use dev_err() instead of dev_dbg()] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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1 changed files with 15 additions and 3 deletions
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@ -31,7 +31,12 @@
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#define LINK_WAIT_USLEEP_MIN 90000
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#define LINK_WAIT_USLEEP_MAX 100000
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/* Synopsis specific PCIE configuration registers */
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/* Parameters for the waiting for iATU enabled routine */
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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#define LINK_WAIT_IATU_MIN 9000
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#define LINK_WAIT_IATU_MAX 10000
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/* Synopsys-specific PCIe configuration registers */
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_MODE_MASK (0x3f << 16)
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#define PORT_LINK_MODE_1_LANES (0x1 << 16)
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@ -157,7 +162,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
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int type, u64 cpu_addr, u64 pci_addr, u32 size)
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{
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u32 val;
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u32 retries, val;
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dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
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PCIE_ATU_VIEWPORT);
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@ -174,7 +179,14 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2);
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2);
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if (val == PCIE_ATU_ENABLE)
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return;
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usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
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}
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dev_err(pp->dev, "iATU is not being enabled\n");
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}
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static struct irq_chip dw_msi_irq_chip = {
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