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Blackfin SPI driver: use cpu_relax() to replace continue in while busywait
Signed-off-by: Bryan Wu <bryan.wu@analog.com> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
parent
07612e5f22
commit
d8c05008b0
1 changed files with 39 additions and 39 deletions
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@ -186,7 +186,7 @@ static int flush(struct driver_data *drv_data)
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/* wait for stop and clear stat */
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/* wait for stop and clear stat */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
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continue;
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cpu_relax();
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write_STAT(drv_data, BIT_STAT_CLR);
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write_STAT(drv_data, BIT_STAT_CLR);
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@ -262,7 +262,7 @@ static void null_writer(struct driver_data *drv_data)
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while (drv_data->tx < drv_data->tx_end) {
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while (drv_data->tx < drv_data->tx_end) {
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write_TDBR(drv_data, 0);
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write_TDBR(drv_data, 0);
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while ((read_STAT(drv_data) & BIT_STAT_TXS))
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while ((read_STAT(drv_data) & BIT_STAT_TXS))
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continue;
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cpu_relax();
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drv_data->tx += n_bytes;
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drv_data->tx += n_bytes;
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}
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}
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}
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}
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@ -274,7 +274,7 @@ static void null_reader(struct driver_data *drv_data)
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while (drv_data->rx < drv_data->rx_end) {
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while (drv_data->rx < drv_data->rx_end) {
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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dummy_read(drv_data);
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dummy_read(drv_data);
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drv_data->rx += n_bytes;
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drv_data->rx += n_bytes;
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}
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}
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@ -287,12 +287,12 @@ static void u8_writer(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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while (drv_data->tx < drv_data->tx_end) {
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while (drv_data->tx < drv_data->tx_end) {
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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continue;
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cpu_relax();
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++drv_data->tx;
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++drv_data->tx;
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}
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}
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}
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}
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@ -303,14 +303,14 @@ static void u8_cs_chg_writer(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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while (drv_data->tx < drv_data->tx_end) {
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while (drv_data->tx < drv_data->tx_end) {
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cs_active(drv_data, chip);
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cs_active(drv_data, chip);
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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continue;
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cpu_relax();
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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@ -325,7 +325,7 @@ static void u8_reader(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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/* clear TDBR buffer before read(else it will be shifted out) */
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/* clear TDBR buffer before read(else it will be shifted out) */
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write_TDBR(drv_data, 0xFFFF);
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write_TDBR(drv_data, 0xFFFF);
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@ -334,13 +334,13 @@ static void u8_reader(struct driver_data *drv_data)
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while (drv_data->rx < drv_data->rx_end - 1) {
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while (drv_data->rx < drv_data->rx_end - 1) {
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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++drv_data->rx;
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++drv_data->rx;
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}
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}
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u8 *) (drv_data->rx) = read_SHAW(drv_data);
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*(u8 *) (drv_data->rx) = read_SHAW(drv_data);
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++drv_data->rx;
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++drv_data->rx;
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}
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}
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@ -351,7 +351,7 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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/* clear TDBR buffer before read(else it will be shifted out) */
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/* clear TDBR buffer before read(else it will be shifted out) */
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write_TDBR(drv_data, 0xFFFF);
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write_TDBR(drv_data, 0xFFFF);
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@ -363,7 +363,7 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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cs_active(drv_data, chip);
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cs_active(drv_data, chip);
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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++drv_data->rx;
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++drv_data->rx;
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@ -371,7 +371,7 @@ static void u8_cs_chg_reader(struct driver_data *drv_data)
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u8 *) (drv_data->rx) = read_SHAW(drv_data);
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*(u8 *) (drv_data->rx) = read_SHAW(drv_data);
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++drv_data->rx;
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++drv_data->rx;
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}
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}
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@ -380,15 +380,15 @@ static void u8_duplex(struct driver_data *drv_data)
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{
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{
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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/* in duplex mode, clk is triggered by writing of TDBR */
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/* in duplex mode, clk is triggered by writing of TDBR */
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while (drv_data->rx < drv_data->rx_end) {
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while (drv_data->rx < drv_data->rx_end) {
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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continue;
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cpu_relax();
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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++drv_data->rx;
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++drv_data->rx;
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++drv_data->tx;
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++drv_data->tx;
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@ -401,16 +401,16 @@ static void u8_cs_chg_duplex(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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while (drv_data->rx < drv_data->rx_end) {
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while (drv_data->rx < drv_data->rx_end) {
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cs_active(drv_data, chip);
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cs_active(drv_data, chip);
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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continue;
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cpu_relax();
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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@ -427,12 +427,12 @@ static void u16_writer(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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while (drv_data->tx < drv_data->tx_end) {
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while (drv_data->tx < drv_data->tx_end) {
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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while ((read_STAT(drv_data) & BIT_STAT_TXS))
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while ((read_STAT(drv_data) & BIT_STAT_TXS))
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continue;
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cpu_relax();
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drv_data->tx += 2;
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drv_data->tx += 2;
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}
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}
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}
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}
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@ -443,14 +443,14 @@ static void u16_cs_chg_writer(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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while (drv_data->tx < drv_data->tx_end) {
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while (drv_data->tx < drv_data->tx_end) {
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cs_active(drv_data, chip);
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cs_active(drv_data, chip);
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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while ((read_STAT(drv_data) & BIT_STAT_TXS))
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while ((read_STAT(drv_data) & BIT_STAT_TXS))
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continue;
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cpu_relax();
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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@ -465,7 +465,7 @@ static void u16_reader(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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/* clear TDBR buffer before read(else it will be shifted out) */
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/* clear TDBR buffer before read(else it will be shifted out) */
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write_TDBR(drv_data, 0xFFFF);
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write_TDBR(drv_data, 0xFFFF);
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@ -474,13 +474,13 @@ static void u16_reader(struct driver_data *drv_data)
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while (drv_data->rx < (drv_data->rx_end - 2)) {
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while (drv_data->rx < (drv_data->rx_end - 2)) {
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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drv_data->rx += 2;
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drv_data->rx += 2;
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}
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}
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_SHAW(drv_data);
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*(u16 *) (drv_data->rx) = read_SHAW(drv_data);
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drv_data->rx += 2;
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drv_data->rx += 2;
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}
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}
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@ -491,7 +491,7 @@ static void u16_cs_chg_reader(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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/* clear TDBR buffer before read(else it will be shifted out) */
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/* clear TDBR buffer before read(else it will be shifted out) */
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write_TDBR(drv_data, 0xFFFF);
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write_TDBR(drv_data, 0xFFFF);
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@ -503,7 +503,7 @@ static void u16_cs_chg_reader(struct driver_data *drv_data)
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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cs_active(drv_data, chip);
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cs_active(drv_data, chip);
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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drv_data->rx += 2;
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drv_data->rx += 2;
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@ -511,7 +511,7 @@ static void u16_cs_chg_reader(struct driver_data *drv_data)
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_SHAW(drv_data);
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*(u16 *) (drv_data->rx) = read_SHAW(drv_data);
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drv_data->rx += 2;
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drv_data->rx += 2;
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}
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}
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@ -520,15 +520,15 @@ static void u16_duplex(struct driver_data *drv_data)
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{
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{
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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/* in duplex mode, clk is triggered by writing of TDBR */
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/* in duplex mode, clk is triggered by writing of TDBR */
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while (drv_data->tx < drv_data->tx_end) {
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while (drv_data->tx < drv_data->tx_end) {
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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continue;
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cpu_relax();
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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drv_data->rx += 2;
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drv_data->rx += 2;
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drv_data->tx += 2;
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drv_data->tx += 2;
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@ -541,16 +541,16 @@ static void u16_cs_chg_duplex(struct driver_data *drv_data)
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/* poll for SPI completion before start */
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/* poll for SPI completion before start */
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
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continue;
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cpu_relax();
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while (drv_data->tx < drv_data->tx_end) {
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while (drv_data->tx < drv_data->tx_end) {
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cs_active(drv_data, chip);
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cs_active(drv_data, chip);
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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while (read_STAT(drv_data) & BIT_STAT_TXS)
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continue;
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cpu_relax();
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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continue;
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cpu_relax();
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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cs_deactive(drv_data, chip);
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cs_deactive(drv_data, chip);
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@ -624,7 +624,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
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/* Wait for DMA to complete */
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/* Wait for DMA to complete */
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while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
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while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
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||||||
continue;
|
cpu_relax();
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* wait for the last transaction shifted out. HRM states:
|
* wait for the last transaction shifted out. HRM states:
|
||||||
|
@ -635,11 +635,11 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
|
||||||
if (drv_data->tx != NULL) {
|
if (drv_data->tx != NULL) {
|
||||||
while ((read_STAT(drv_data) & TXS) ||
|
while ((read_STAT(drv_data) & TXS) ||
|
||||||
(read_STAT(drv_data) & TXS))
|
(read_STAT(drv_data) & TXS))
|
||||||
continue;
|
cpu_relax();
|
||||||
}
|
}
|
||||||
|
|
||||||
while (!(read_STAT(drv_data) & SPIF))
|
while (!(read_STAT(drv_data) & SPIF))
|
||||||
continue;
|
cpu_relax();
|
||||||
|
|
||||||
msg->actual_length += drv_data->len_in_bytes;
|
msg->actual_length += drv_data->len_in_bytes;
|
||||||
|
|
||||||
|
@ -783,7 +783,7 @@ static void pump_transfers(unsigned long data)
|
||||||
|
|
||||||
/* poll for SPI completion before start */
|
/* poll for SPI completion before start */
|
||||||
while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
|
while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
|
||||||
continue;
|
cpu_relax();
|
||||||
|
|
||||||
/* dirty hack for autobuffer DMA mode */
|
/* dirty hack for autobuffer DMA mode */
|
||||||
if (drv_data->tx_dma == 0xFFFF) {
|
if (drv_data->tx_dma == 0xFFFF) {
|
||||||
|
|
Loading…
Reference in a new issue