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arm64: dts: qcom: sm8150: Add apps shared nodes
Add hwlock, pmu, smem, tcsr_mutex_regs, apss_shared mailbox, apps_rsc including the rpmhcc child nodes to the SM8150 DTSI Co-developed-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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1 changed files with 63 additions and 0 deletions
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@ -144,12 +144,23 @@ scm: scm {
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x1000>;
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#hwlock-cells = <1>;
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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@ -266,6 +277,12 @@ qseecom_mem: memory@9e400000 {
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -306,6 +323,11 @@ uart2: serial@a90000 {
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};
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};
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tcsr_mutex_regs: syscon@1f40000 {
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compatible = "syscon";
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reg = <0x0 0x01f40000 0x0 0x40000>;
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};
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tlmm: pinctrl@3100000 {
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compatible = "qcom,sm8150-pinctrl";
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reg = <0x0 0x03100000 0x0 0x300000>,
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@ -321,6 +343,16 @@ tlmm: pinctrl@3100000 {
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#interrupt-cells = <2>;
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};
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aoss_qmp: power-controller@c300000 {
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compatible = "qcom,sm8150-aoss-qmp";
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reg = <0x0 0x0c300000 0x0 0x100000>;
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interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apss_shared 0>;
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#clock-cells = <0>;
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#power-domain-cells = <1>;
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};
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spmi_bus: spmi@c440000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x0 0x0c440000 0x0 0x0001100>,
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@ -349,6 +381,12 @@ intc: interrupt-controller@17a00000 {
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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apss_shared: mailbox@17c00000 {
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compatible = "qcom,sm8150-apss-shared";
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reg = <0x0 0x17c00000 0x0 0x1000>;
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#mbox-cells = <1>;
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};
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timer@17c20000 {
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#address-cells = <2>;
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#size-cells = <2>;
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@ -407,6 +445,31 @@ frame@17c2d000 {
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status = "disabled";
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};
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};
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apps_rsc: rsc@18200000 {
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label = "apps_rsc";
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compatible = "qcom,rpmh-rsc";
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reg = <0x0 0x18200000 0x0 0x10000>,
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<0x0 0x18210000 0x0 0x10000>,
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<0x0 0x18220000 0x0 0x10000>;
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reg-names = "drv-0", "drv-1", "drv-2";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <2>;
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qcom,tcs-config = <ACTIVE_TCS 2>,
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<SLEEP_TCS 1>,
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<WAKE_TCS 1>,
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<CONTROL_TCS 0>;
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rpmhcc: clock-controller {
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compatible = "qcom,sm8150-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board>;
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};
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};
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};
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timer {
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