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platform/x86:intel/pmc: Add support to show S0ix blocker counter
S0ix blocker counter is available in PWRM space. Add support to read and show S0ix blocker counter value through debugfs. Signed-off-by: Xi Pardee <xi.pardee@intel.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20240426002752.2504282-3-xi.pardee@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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2 changed files with 44 additions and 0 deletions
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@ -678,6 +678,41 @@ static int pmc_core_ltr_show(struct seq_file *s, void *unused)
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}
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DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
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static int pmc_core_s0ix_blocker_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmcdev = s->private;
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unsigned int pmcidx;
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for (pmcidx = 0; pmcidx < ARRAY_SIZE(pmcdev->pmcs); pmcidx++) {
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const struct pmc_bit_map **maps;
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unsigned int arr_size, r_idx;
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u32 offset, counter;
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struct pmc *pmc;
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pmc = pmcdev->pmcs[pmcidx];
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if (!pmc)
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continue;
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maps = pmc->map->s0ix_blocker_maps;
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offset = pmc->map->s0ix_blocker_offset;
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arr_size = pmc_core_lpm_get_arr_size(maps);
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for (r_idx = 0; r_idx < arr_size; r_idx++) {
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const struct pmc_bit_map *map;
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for (map = maps[r_idx]; map->name; map++) {
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if (!map->blk)
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continue;
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counter = pmc_core_reg_read(pmc, offset);
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seq_printf(s, "PMC%d:%-30s %-30d\n", pmcidx,
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map->name, counter);
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offset += map->blk * S0IX_BLK_SIZE;
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}
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}
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}
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(pmc_core_s0ix_blocker);
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static inline u64 adjust_lpm_residency(struct pmc *pmc, u32 offset,
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const int lpm_adj_x2)
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{
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@ -1197,6 +1232,9 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
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debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
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if (primary_pmc->map->s0ix_blocker_maps)
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debugfs_create_file("s0ix_blocker", 0444, dir, pmcdev, &pmc_core_s0ix_blocker_fops);
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debugfs_create_file("package_cstate_show", 0444, dir, primary_pmc,
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&pmc_core_pkgc_fops);
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@ -22,6 +22,7 @@ struct telem_endpoint;
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#define PMC_BASE_ADDR_DEFAULT 0xFE000000
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#define MAX_NUM_PMC 3
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#define S0IX_BLK_SIZE 4
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/* Sunrise Point Power Management Controller PCI Device ID */
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#define SPT_PMC_PCI_DEVICE_ID 0x9d21
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@ -288,6 +289,7 @@ extern const char *pmc_lpm_modes[];
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struct pmc_bit_map {
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const char *name;
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u32 bit_mask;
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u8 blk;
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};
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/**
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@ -298,6 +300,7 @@ struct pmc_bit_map {
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* @pll_sts: Maps name of PLL to corresponding bit status
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* @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info
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* @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets
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* @s0ix_blocker_maps: Maps name of IP block to S0ix blocker counter
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* @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
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* @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
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* @regmap_length: Length of memory to map from PWRMBASE address to access
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@ -307,6 +310,7 @@ struct pmc_bit_map {
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* @pm_cfg_offset: PWRMBASE offset to PM_CFG register
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* @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
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* @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG*
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* @s0ix_blocker_offset PWRMBASE offset to S0ix blocker counter
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*
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* Each PCH has unique set of register offsets and bit indexes. This structure
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* captures them to have a common implementation.
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@ -319,6 +323,7 @@ struct pmc_reg_map {
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const struct pmc_bit_map *ltr_show_sts;
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const struct pmc_bit_map *msr_sts;
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const struct pmc_bit_map **lpm_sts;
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const struct pmc_bit_map **s0ix_blocker_maps;
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const u32 slp_s0_offset;
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const int slp_s0_res_counter_step;
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const u32 ltr_ignore_offset;
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@ -330,6 +335,7 @@ struct pmc_reg_map {
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const u32 slps0_dbg_offset;
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const u32 ltr_ignore_max;
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const u32 pm_vric1_offset;
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const u32 s0ix_blocker_offset;
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/* Low Power Mode registers */
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const int lpm_num_maps;
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const int lpm_num_modes;
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