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Blackfin arch: add BF54x I2C/TWI TWI0 driver support
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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commit
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3 changed files with 36 additions and 2 deletions
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@ -92,9 +92,9 @@ config I2C_AU1550
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config I2C_BLACKFIN_TWI
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tristate "Blackfin TWI I2C support"
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depends on BF534 || BF536 || BF537
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depends on BF534 || BF536 || BF537 || BF54x
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help
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This is the TWI I2C device driver for Blackfin 534/536/537.
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This is the TWI I2C device driver for Blackfin 534/536/537/54x.
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This driver can also be built as a module. If so, the module
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will be called i2c-bfin-twi.
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@ -242,6 +242,39 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
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#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
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#define bfin_read_TWI_CLKDIV() bfin_read16(TWI0_CLKDIV)
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#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
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#define bfin_read_TWI_CONTROL() bfin_read16(TWI0_CONTROL)
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#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
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#define bfin_read_TWI_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
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#define bfin_write_TWI_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
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#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
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#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
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#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
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#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
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#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI0_MASTER_CTRL)
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#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTRL, val)
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#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
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#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
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#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
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#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
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#define bfin_read_TWI_INT_STAT() bfin_read16(TWI0_INT_STAT)
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#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
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#define bfin_read_TWI_INT_MASK() bfin_read16(TWI0_INT_MASK)
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#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
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#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI0_FIFO_CTRL)
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#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTRL, val)
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#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
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#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
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#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
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#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
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#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
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#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
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#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
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#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
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#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
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#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
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/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
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/* SPORT1 Registers */
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@ -112,6 +112,7 @@ Events (highest priority) EMU 0
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#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
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#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
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#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
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#define IRQ_TWI IRQ_TWI0 /* TWI Interrupt */
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#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
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#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
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#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
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