From 4b9b7b3a2c91e1ebf8be9c7efd4839b91d66e87e Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 12 Jul 2016 00:51:58 +0300 Subject: [PATCH 1/2] ARM: dts: r8a7792: add PLL1 divided by 2 clock Despite the fact that QSPI clock has PLL1/VCOx1/4 clock as a parent, the latter hasn't been added to the R8A7792 device tree. This patch corrects that oversight. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 75256ef4a04d..d5fd0762e2d6 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -284,6 +284,13 @@ cpg_clocks: cpg_clocks@e6150000 { }; /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; From e0c3f92a08f3e0a95024d0d032564fdc1ee96f54 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 12 Jul 2016 00:52:43 +0300 Subject: [PATCH 2/2] ARM: dts: r8a7792: remove ADSP clock Simon Horman told me that R8A7792 has ADSP clock based on an incorrect table in the most recent R-Car gen2 manual. But when I received that manual I discovered that this is false: R8A7792 is the only Gen 2 SoC that doesn't have ADSP at all. Accordingly remove the ADSP clock from DT for the r8a7792. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 2 +- include/dt-bindings/clock/r8a7792-clock.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index d5fd0762e2d6..3fd61d7ab906 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -279,7 +279,7 @@ cpg_clocks: cpg_clocks@e6150000 { clocks = <&extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "z", "adsp"; + "lb", "qspi", "z"; #power-domain-cells = <0>; }; diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h index 89a5155913f6..9a8b392ceb00 100644 --- a/include/dt-bindings/clock/r8a7792-clock.h +++ b/include/dt-bindings/clock/r8a7792-clock.h @@ -18,7 +18,6 @@ #define R8A7792_CLK_LB 4 #define R8A7792_CLK_QSPI 5 #define R8A7792_CLK_Z 6 -#define R8A7792_CLK_ADSP 7 /* MSTP0 */ #define R8A7792_CLK_MSIOF0 0