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drm/amdgpu: implement gmc_v7_0_emit_flush_gpu_tlb
Unify tlb flushing for gmc v7. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4fef88bd00
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4 changed files with 26 additions and 35 deletions
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@ -24,6 +24,8 @@
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#ifndef __CIK_H__
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#define __CIK_H__
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#define CIK_FLUSH_GPU_TLB_NUM_WREG 2
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void cik_srbm_select(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue, u32 vmid);
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int cik_set_ip_blocks(struct amdgpu_device *adev);
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@ -886,18 +886,7 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
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u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
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SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
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amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
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if (vmid < 8) {
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amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
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} else {
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amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
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}
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amdgpu_ring_write(ring, pd_addr >> 12);
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/* flush TLB */
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amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
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amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
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amdgpu_ring_write(ring, 1 << vmid);
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amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
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amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
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amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
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@ -1290,7 +1279,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
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6 + /* cik_sdma_ring_emit_hdp_flush */
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3 + /* cik_sdma_ring_emit_hdp_invalidate */
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6 + /* cik_sdma_ring_emit_pipeline_sync */
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12 + /* cik_sdma_ring_emit_vm_flush */
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CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
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9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
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.emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
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.emit_ib = cik_sdma_ring_emit_ib,
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@ -3244,26 +3244,7 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
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{
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int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
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WRITE_DATA_DST_SEL(0)));
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if (vmid < 8) {
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amdgpu_ring_write(ring,
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(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
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} else {
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amdgpu_ring_write(ring,
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(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
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}
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, pd_addr >> 12);
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/* bits 0-15 are the VM contexts0-15 */
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amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
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WRITE_DATA_DST_SEL(0)));
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amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
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amdgpu_ring_write(ring, 0);
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amdgpu_ring_write(ring, 1 << vmid);
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amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr);
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/* wait for the invalidate to complete */
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amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
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@ -5132,7 +5113,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
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5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
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12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */
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7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */
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17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
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CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */
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3 + 4, /* gfx_v7_ring_emit_cntxcntl including vgt flush*/
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.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */
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.emit_ib = gfx_v7_0_ring_emit_ib_gfx,
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@ -5163,7 +5144,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
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7 + /* gfx_v7_0_ring_emit_hdp_flush */
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5 + /* gfx_v7_0_ring_emit_hdp_invalidate */
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7 + /* gfx_v7_0_ring_emit_pipeline_sync */
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17 + /* gfx_v7_0_ring_emit_vm_flush */
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CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */
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7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */
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.emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */
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.emit_ib = gfx_v7_0_ring_emit_ib_compute,
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@ -435,6 +435,24 @@ static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
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WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
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}
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static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
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unsigned vmid, unsigned pasid,
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uint64_t pd_addr)
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{
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uint32_t reg;
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if (vmid < 8)
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reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
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else
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reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
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amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
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/* bits 0-15 are the VM contexts0-15 */
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amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
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return pd_addr;
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}
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/**
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* gmc_v7_0_set_pte_pde - update the page tables using MMIO
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*
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@ -1305,6 +1323,7 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
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static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
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.flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
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.emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
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.set_pte_pde = gmc_v7_0_set_pte_pde,
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.set_prt = gmc_v7_0_set_prt,
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.get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags,
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