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drm/amdgpu: add unified queue support on vcn_v4_0_3
Add unified queue support on vcn_v4_0_3. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
2d7f1d51c1
commit
da044aaeb3
2 changed files with 102 additions and 80 deletions
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@ -1004,11 +1004,14 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
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int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
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{
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struct amdgpu_device *adev = ring->adev;
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long r;
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r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
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if (r)
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goto error;
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if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(4, 0, 3)) {
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r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
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if (r)
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goto error;
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}
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r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
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@ -31,7 +31,6 @@
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#include "soc15d.h"
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#include "soc15_hw_ip.h"
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#include "vcn_v2_0.h"
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#include "vcn_sw_ring.h"
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#include "vcn/vcn_4_0_3_offset.h"
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#include "vcn/vcn_4_0_3_sh_mask.h"
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@ -45,12 +44,13 @@
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#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
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#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
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static void vcn_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);
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static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
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static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
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static int vcn_v4_0_3_set_powergating_state(void *handle,
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enum amd_powergating_state state);
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static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
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int inst_idx, struct dpg_pause_state *new_state);
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static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring);
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/**
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* vcn_v4_0_3_early_init - set function pointers
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@ -63,7 +63,10 @@ static int vcn_v4_0_3_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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vcn_v4_0_3_set_dec_ring_funcs(adev);
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/* re-use enc ring as unified ring */
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adev->vcn.num_enc_rings = 1;
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vcn_v4_0_3_set_unified_ring_funcs(adev);
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vcn_v4_0_3_set_irq_funcs(adev);
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return 0;
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@ -94,7 +97,7 @@ static int vcn_v4_0_3_sw_init(void *handle)
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/* VCN DEC TRAP */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
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VCN_4_0__SRCID__UVD_TRAP, &adev->vcn.inst->irq);
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VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);
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if (r)
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return r;
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@ -104,11 +107,11 @@ static int vcn_v4_0_3_sw_init(void *handle)
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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ring = &adev->vcn.inst[i].ring_dec;
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ring = &adev->vcn.inst[i].ring_enc[0];
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ring->use_doorbell = true;
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ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * i;
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ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
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sprintf(ring->name, "vcn_dec_%d", i);
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sprintf(ring->name, "vcn_unified_%d", i);
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r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
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AMDGPU_RING_PRIO_DEFAULT,
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&adev->vcn.inst[i].sched_score);
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@ -116,7 +119,7 @@ static int vcn_v4_0_3_sw_init(void *handle)
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return r;
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fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
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fw_shared->present_flag_0 = 0;
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fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
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fw_shared->sq.is_enabled = cpu_to_le32(true);
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if (amdgpu_vcnfw_log)
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@ -179,17 +182,17 @@ static int vcn_v4_0_3_hw_init(void *handle)
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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ring = &adev->vcn.inst[i].ring_dec;
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ring = &adev->vcn.inst[i].ring_enc[0];
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if (ring->use_doorbell)
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if (ring->use_doorbell) {
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adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
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(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * i,
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adev->vcn.inst[i].aid_id);
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if (ring->use_doorbell)
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WREG32_SOC15(VCN, ring->me, regVCN_RB4_DB_CTRL,
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ring->doorbell_index << VCN_RB4_DB_CTRL__OFFSET__SHIFT |
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VCN_RB4_DB_CTRL__EN_MASK);
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WREG32_SOC15(VCN, ring->me, regVCN_RB1_DB_CTRL,
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ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
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VCN_RB1_DB_CTRL__EN_MASK);
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}
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r = amdgpu_ring_test_helper(ring);
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if (r)
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@ -731,31 +734,31 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
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(uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
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(uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
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ring = &adev->vcn.inst[inst_idx].ring_dec;
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ring = &adev->vcn.inst[inst_idx].ring_enc[0];
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/* program the RB_BASE for ring buffer */
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO4,
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO,
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lower_32_bits(ring->gpu_addr));
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI4,
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI,
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upper_32_bits(ring->gpu_addr));
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE4, ring->ring_size / sizeof(uint32_t));
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t));
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/* resetting ring, fw should not check RB ring */
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tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
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tmp &= ~(VCN_RB_ENABLE__RB4_EN_MASK);
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tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
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WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
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fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
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/* Initialize the ring buffer's read and write pointers */
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR4, 0);
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4, 0);
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ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4);
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
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WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
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ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
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tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
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tmp |= VCN_RB_ENABLE__RB4_EN_MASK;
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tmp |= VCN_RB_ENABLE__RB_EN_MASK;
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WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
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WREG32_SOC15(VCN, inst_idx, regUVD_SCRATCH2, 0);
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fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
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/*resetting done, fw can check RB ring */
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fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
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@ -902,31 +905,31 @@ static int vcn_v4_0_3_start(struct amdgpu_device *adev)
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WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
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~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
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ring = &adev->vcn.inst[i].ring_dec;
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ring = &adev->vcn.inst[i].ring_enc[0];
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fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
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/* program the RB_BASE for ring buffer */
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WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO4,
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WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO,
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lower_32_bits(ring->gpu_addr));
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WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI4,
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WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI,
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upper_32_bits(ring->gpu_addr));
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WREG32_SOC15(VCN, i, regUVD_RB_SIZE4, ring->ring_size / sizeof(uint32_t));
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WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t));
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/* resetting ring, fw should not check RB ring */
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tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
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tmp &= ~(VCN_RB_ENABLE__RB4_EN_MASK);
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tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
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WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
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/* Initialize the ring buffer's read and write pointers */
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WREG32_SOC15(VCN, i, regUVD_RB_RPTR4, 0);
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WREG32_SOC15(VCN, i, regUVD_RB_WPTR4, 0);
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WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
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WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
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tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
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tmp |= VCN_RB_ENABLE__RB4_EN_MASK;
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tmp |= VCN_RB_ENABLE__RB_EN_MASK;
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WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
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ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR4);
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ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
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fw_shared->sq.queue_mode &=
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cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
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@ -951,8 +954,8 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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/* wait for read ptr to be equal to write ptr */
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tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR4);
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SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR4, tmp, 0xFFFFFFFF);
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tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
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SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
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SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
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@ -972,15 +975,20 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
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*/
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static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
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{
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volatile struct amdgpu_vcn4_fw_shared *fw_shared;
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uint32_t tmp;
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int i, r = 0;
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for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
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if (adev->vcn.harvest_config & (1 << i))
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continue;
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fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
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fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
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if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
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r = vcn_v4_0_3_stop_dpg_mode(adev, i);
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goto Done;
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vcn_v4_0_3_stop_dpg_mode(adev, i);
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continue;
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}
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/* wait for vcn idle */
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@ -1000,7 +1008,7 @@ static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
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tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
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tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
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WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
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tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
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tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
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UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
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r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
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if (r)
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@ -1059,101 +1067,112 @@ static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
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}
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/**
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* vcn_v4_0_3_dec_ring_get_rptr - get read pointer
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* vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware read pointer
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* Returns the current hardware unified read pointer
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*/
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static uint64_t vcn_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring)
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static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR4);
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if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
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DRM_ERROR("wrong ring id is identified in %s", __func__);
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return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
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}
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/**
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* vcn_v4_0_3_dec_ring_get_wptr - get write pointer
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* vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware write pointer
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* Returns the current hardware unified write pointer
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*/
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static uint64_t vcn_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring)
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static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
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DRM_ERROR("wrong ring id is identified in %s", __func__);
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if (ring->use_doorbell)
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return adev->wb.wb[ring->wptr_offs];
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return *ring->wptr_cpu_addr;
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else
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return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR4);
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return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
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}
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/**
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* vcn_v4_0_3_dec_ring_set_wptr - set write pointer
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* vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the write pointer to the hardware
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* Commits the enc write pointer to the hardware
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*/
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static void vcn_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring)
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static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
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DRM_ERROR("wrong ring id is identified in %s", __func__);
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if (ring->use_doorbell) {
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adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
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*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
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WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
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} else {
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WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR4, lower_32_bits(ring->wptr));
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WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
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}
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}
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static const struct amdgpu_ring_funcs vcn_v4_0_3_dec_sw_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_DEC,
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static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {
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.type = AMDGPU_RING_TYPE_VCN_ENC,
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.align_mask = 0x3f,
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.nop = VCN_DEC_SW_CMD_NO_OP,
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.get_rptr = vcn_v4_0_3_dec_ring_get_rptr,
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.get_wptr = vcn_v4_0_3_dec_ring_get_wptr,
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.set_wptr = vcn_v4_0_3_dec_ring_set_wptr,
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.nop = VCN_ENC_CMD_NO_OP,
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.get_rptr = vcn_v4_0_3_unified_ring_get_rptr,
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.get_wptr = vcn_v4_0_3_unified_ring_get_wptr,
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.set_wptr = vcn_v4_0_3_unified_ring_set_wptr,
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.emit_frame_size =
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SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
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SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
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VCN_SW_RING_EMIT_FRAME_SIZE,
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.emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */
|
||||
.emit_ib = vcn_dec_sw_ring_emit_ib,
|
||||
.emit_fence = vcn_dec_sw_ring_emit_fence,
|
||||
.emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush,
|
||||
.test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
|
||||
.test_ib = amdgpu_vcn_dec_sw_ring_test_ib,
|
||||
4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
|
||||
5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
|
||||
1, /* vcn_v2_0_enc_ring_insert_end */
|
||||
.emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
|
||||
.emit_ib = vcn_v2_0_enc_ring_emit_ib,
|
||||
.emit_fence = vcn_v2_0_enc_ring_emit_fence,
|
||||
.emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
|
||||
.test_ring = amdgpu_vcn_enc_ring_test_ring,
|
||||
.test_ib = amdgpu_vcn_unified_ring_test_ib,
|
||||
.insert_nop = amdgpu_ring_insert_nop,
|
||||
.insert_end = vcn_dec_sw_ring_insert_end,
|
||||
.insert_end = vcn_v2_0_enc_ring_insert_end,
|
||||
.pad_ib = amdgpu_ring_generic_pad_ib,
|
||||
.begin_use = amdgpu_vcn_ring_begin_use,
|
||||
.end_use = amdgpu_vcn_ring_end_use,
|
||||
.emit_wreg = vcn_dec_sw_ring_emit_wreg,
|
||||
.emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait,
|
||||
.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
|
||||
.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
|
||||
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
|
||||
};
|
||||
|
||||
/**
|
||||
* vcn_v4_0_3_set_dec_ring_funcs - set dec ring functions
|
||||
* vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
*
|
||||
* Set decode ring functions
|
||||
* Set unified ring functions
|
||||
*/
|
||||
static void vcn_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev)
|
||||
static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
|
||||
if (adev->vcn.harvest_config & (1 << i))
|
||||
continue;
|
||||
adev->vcn.inst[i].ring_dec.funcs = &vcn_v4_0_3_dec_sw_ring_vm_funcs;
|
||||
adev->vcn.inst[i].ring_dec.me = i;
|
||||
adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;
|
||||
adev->vcn.inst[i].ring_enc[0].me = i;
|
||||
adev->vcn.inst[i].aid_id = i / adev->vcn.num_inst_per_aid;
|
||||
}
|
||||
DRM_DEV_INFO(adev->dev, "VCN decode(Software Ring) is enabled in VM mode\n");
|
||||
DRM_DEV_INFO(adev->dev, "VCN decode is enabled in VM mode\n");
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -1276,7 +1295,7 @@ static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev,
|
|||
}
|
||||
|
||||
/**
|
||||
* vcn_v4_0_process_interrupt - process VCN block interrupt
|
||||
* vcn_v4_0_3_process_interrupt - process VCN block interrupt
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
* @source: interrupt sources
|
||||
|
@ -1295,8 +1314,8 @@ static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev,
|
|||
DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n");
|
||||
|
||||
switch (entry->src_id) {
|
||||
case VCN_4_0__SRCID__UVD_TRAP:
|
||||
amdgpu_fence_process(&adev->vcn.inst[i].ring_dec);
|
||||
case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
|
||||
amdgpu_fence_process(&adev->vcn.inst[i].ring_enc[0]);
|
||||
break;
|
||||
default:
|
||||
DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
|
||||
|
|
Loading…
Reference in a new issue