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sata_mv ncq Use DMA memory pools for hardware memory tables
Create host-owned DMA memory pools, for use in allocating/freeing per-port command/response queues and SG tables. This gives us a way to guarantee we meet the hardware address alignment requirements, and also reduces memory that might otherwise be wasted on alignment gaps. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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f273827e2a
commit
da2fa9baf0
1 changed files with 70 additions and 32 deletions
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@ -107,14 +107,12 @@ enum {
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/* CRQB needs alignment on a 1KB boundary. Size == 1KB
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* CRPB needs alignment on a 256B boundary. Size == 256B
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* SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
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* ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
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*/
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MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
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MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
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MV_MAX_SG_CT = 176,
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MV_MAX_SG_CT = 256,
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MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
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MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
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MV_PORTS_PER_HC = 4,
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/* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
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@ -421,6 +419,14 @@ struct mv_host_priv {
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u32 irq_cause_ofs;
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u32 irq_mask_ofs;
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u32 unmask_all_irqs;
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/*
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* These consistent DMA memory pools give us guaranteed
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* alignment for hardware-accessed data structures,
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* and less memory waste in accomplishing the alignment.
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*/
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struct dma_pool *crqb_pool;
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struct dma_pool *crpb_pool;
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struct dma_pool *sg_tbl_pool;
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};
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struct mv_hw_ops {
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@ -1097,6 +1103,25 @@ static void mv_edma_cfg(struct mv_port_priv *pp, struct mv_host_priv *hpriv,
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writelfl(cfg, port_mmio + EDMA_CFG_OFS);
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}
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static void mv_port_free_dma_mem(struct ata_port *ap)
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{
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struct mv_host_priv *hpriv = ap->host->private_data;
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struct mv_port_priv *pp = ap->private_data;
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if (pp->crqb) {
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dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
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pp->crqb = NULL;
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}
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if (pp->crpb) {
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dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
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pp->crpb = NULL;
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}
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if (pp->sg_tbl) {
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dma_pool_free(hpriv->sg_tbl_pool, pp->sg_tbl, pp->sg_tbl_dma);
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pp->sg_tbl = NULL;
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}
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}
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/**
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* mv_port_start - Port specific init/start routine.
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* @ap: ATA channel to manipulate
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@ -1113,51 +1138,36 @@ static int mv_port_start(struct ata_port *ap)
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struct mv_host_priv *hpriv = ap->host->private_data;
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struct mv_port_priv *pp;
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void __iomem *port_mmio = mv_ap_base(ap);
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void *mem;
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dma_addr_t mem_dma;
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unsigned long flags;
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int rc;
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pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
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if (!pp)
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return -ENOMEM;
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mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
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GFP_KERNEL);
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if (!mem)
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return -ENOMEM;
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memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
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ap->private_data = pp;
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rc = ata_pad_alloc(ap, dev);
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if (rc)
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return rc;
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/* First item in chunk of DMA memory:
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* 32-slot command request table (CRQB), 32 bytes each in size
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*/
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pp->crqb = mem;
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pp->crqb_dma = mem_dma;
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mem += MV_CRQB_Q_SZ;
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mem_dma += MV_CRQB_Q_SZ;
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pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
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if (!pp->crqb)
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return -ENOMEM;
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memset(pp->crqb, 0, MV_CRQB_Q_SZ);
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/* Second item:
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* 32-slot command response table (CRPB), 8 bytes each in size
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*/
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pp->crpb = mem;
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pp->crpb_dma = mem_dma;
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mem += MV_CRPB_Q_SZ;
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mem_dma += MV_CRPB_Q_SZ;
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pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
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if (!pp->crpb)
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goto out_port_free_dma_mem;
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memset(pp->crpb, 0, MV_CRPB_Q_SZ);
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/* Third item:
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* Table of scatter-gather descriptors (ePRD), 16 bytes each
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*/
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pp->sg_tbl = mem;
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pp->sg_tbl_dma = mem_dma;
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pp->sg_tbl = dma_pool_alloc(hpriv->sg_tbl_pool, GFP_KERNEL,
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&pp->sg_tbl_dma);
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if (!pp->sg_tbl)
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goto out_port_free_dma_mem;
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spin_lock_irqsave(&ap->host->lock, flags);
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mv_edma_cfg(pp, hpriv, port_mmio, 0);
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mv_set_edma_ptrs(port_mmio, hpriv, pp);
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spin_unlock_irqrestore(&ap->host->lock, flags);
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@ -1166,8 +1176,11 @@ static int mv_port_start(struct ata_port *ap)
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* we'll be unable to send non-data, PIO, etc due to restricted access
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* to shadow regs.
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*/
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ap->private_data = pp;
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return 0;
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out_port_free_dma_mem:
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mv_port_free_dma_mem(ap);
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return -ENOMEM;
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}
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/**
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@ -1182,6 +1195,7 @@ static int mv_port_start(struct ata_port *ap)
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static void mv_port_stop(struct ata_port *ap)
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{
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mv_stop_dma(ap);
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mv_port_free_dma_mem(ap);
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}
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/**
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@ -2765,6 +2779,26 @@ static void mv_print_info(struct ata_host *host)
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scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
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}
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static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
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{
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hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
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MV_CRQB_Q_SZ, 0);
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if (!hpriv->crqb_pool)
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return -ENOMEM;
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hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
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MV_CRPB_Q_SZ, 0);
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if (!hpriv->crpb_pool)
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return -ENOMEM;
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hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
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MV_SG_TBL_SZ, 0);
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if (!hpriv->sg_tbl_pool)
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return -ENOMEM;
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return 0;
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}
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/**
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* mv_init_one - handle a positive probe of a Marvell host
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* @pdev: PCI device found
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@ -2810,6 +2844,10 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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if (rc)
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return rc;
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rc = mv_create_dma_pools(hpriv, &pdev->dev);
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if (rc)
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return rc;
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/* initialize adapter */
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rc = mv_init_host(host, board_idx);
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if (rc)
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