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ARM: 6528/1: Use CTR for the I-cache line size on ARMv7
The current implementation of the v7_coherent_*_range function assumes that the D and I cache lines have the same size, which is incorrect architecturally. This patch adds the icache_line_size macro which reads the CTR register. The main loop in v7_coherent_*_range is split in two independent loops or the D and I caches. This also has the performance advantage that the DSB is moved outside the main loop. Reported-by: Kevin Sapp <ksapp@quicinc.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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2 changed files with 28 additions and 11 deletions
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@ -173,15 +173,22 @@ ENTRY(v7_coherent_user_range)
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UNWIND(.fnstart )
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UNWIND(.fnstart )
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dcache_line_size r2, r3
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dcache_line_size r2, r3
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sub r3, r2, #1
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sub r3, r2, #1
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bic r0, r0, r3
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bic r12, r0, r3
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1:
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1:
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USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification
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USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
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dsb
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add r12, r12, r2
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USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line
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cmp r12, r1
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add r0, r0, r2
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2:
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cmp r0, r1
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blo 1b
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blo 1b
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dsb
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icache_line_size r2, r3
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sub r3, r2, #1
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bic r12, r0, r3
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2:
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USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
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add r12, r12, r2
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cmp r12, r1
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blo 2b
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3:
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mov r0, #0
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mov r0, #0
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ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
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ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
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ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
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ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
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@ -194,10 +201,10 @@ ENTRY(v7_coherent_user_range)
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* isn't mapped, just try the next page.
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* isn't mapped, just try the next page.
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*/
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*/
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9001:
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9001:
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mov r0, r0, lsr #12
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mov r12, r12, lsr #12
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mov r0, r0, lsl #12
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mov r12, r12, lsl #12
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add r0, r0, #4096
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add r12, r12, #4096
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b 2b
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b 3b
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UNWIND(.fnend )
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UNWIND(.fnend )
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ENDPROC(v7_coherent_kern_range)
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ENDPROC(v7_coherent_kern_range)
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ENDPROC(v7_coherent_user_range)
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ENDPROC(v7_coherent_user_range)
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@ -72,6 +72,16 @@
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mov \reg, \reg, lsl \tmp @ actual cache line size
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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.endm
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/*
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* icache_line_size - get the minimum I-cache line size from the CTR register
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* on ARMv7.
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*/
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.macro icache_line_size, reg, tmp
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mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
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and \tmp, \tmp, #0xf @ cache line size encoding
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mov \reg, #4 @ bytes per word
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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/*
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/*
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* Sanity check the PTE configuration for the code below - which makes
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* Sanity check the PTE configuration for the code below - which makes
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