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arm64: entry: simplify kernel_exit logic
For historical reasons, the non-KPTI exception return path is duplicated for EL1 and EL0, with the structure: .if \el == 0 [ KPTI handling ] ldr lr, [sp, #S_LR] add sp, sp, #PT_REGS_SIZE // restore sp [ EL0 exception return workaround ] eret .else ldr lr, [sp, #S_LR] add sp, sp, #PT_REGS_SIZE // restore sp [ EL1 exception return workaround ] eret .endif sb This would be simpler and clearer with the common portions factored out, e.g. .if \el == 0 [ KPTI handling ] .endif ldr lr, [sp, #S_LR] add sp, sp, #PT_REGS_SIZE // restore sp .if \el == 0 [ EL0 exception return workaround ] .else [ EL1 exception return workaround ] .endif eret sb This expands to the same code, but is simpler for a human to follow as it avoids duplicates the restore of LR+SP, and makes it clear that the ERET is associated with the SB. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Rob Herring <robh@kernel.org> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240116110221.420467-3-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org>
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1 changed files with 4 additions and 5 deletions
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@ -442,24 +442,23 @@ alternative_else_nop_endif
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.L_skip_tramp_exit_\@:
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#endif
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.endif
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ldr lr, [sp, #S_LR]
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add sp, sp, #PT_REGS_SIZE // restore sp
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.if \el == 0
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/* This must be after the last explicit memory access */
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alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
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tlbi vale1, xzr
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dsb nsh
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alternative_else_nop_endif
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eret
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.else
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ldr lr, [sp, #S_LR]
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add sp, sp, #PT_REGS_SIZE // restore sp
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/* Ensure any device/NC reads complete */
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alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
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.endif
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eret
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.endif
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sb
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.endm
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