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drm/amdgpu: Rework xgmi_wafl_pcs ras sw_init 

To align with other IP blocks.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Stanley Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2023-03-04 19:54:14 +08:00 committed by Alex Deucher
parent 7f544c5488
commit da9d669eab
4 changed files with 35 additions and 10 deletions
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9
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
View File

@ -479,11 +479,10 @@ int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev)
if (r)
return r;
if (!adev->gmc.xgmi.connected_to_cpu) {
adev->gmc.xgmi.ras = &xgmi_ras;
amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block);
adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm;
}
/* xgmi ras block */
r = amdgpu_xgmi_ras_sw_init(adev);
if (r)
return r;
return 0;
}

28
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
View File

@ -1048,12 +1048,30 @@ struct amdgpu_ras_block_hw_ops xgmi_ras_hw_ops = {
struct amdgpu_xgmi_ras xgmi_ras = {
.ras_block = {
.ras_comm = {
.name = "xgmi_wafl",
.block = AMDGPU_RAS_BLOCK__XGMI_WAFL,
.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
},
.hw_ops = &xgmi_ras_hw_ops,
.ras_late_init = amdgpu_xgmi_ras_late_init,
},
};
int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev)
{
int err;
struct amdgpu_xgmi_ras *ras;
if (!adev->gmc.xgmi.ras)
return 0;
ras = adev->gmc.xgmi.ras;
err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
if (err) {
dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n");
return err;
}
strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl_pcs");
ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm;
return 0;
}

1
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
View File

@ -73,5 +73,6 @@ static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
adev->gmc.xgmi.hive_id &&
adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
}
int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev);
#endif

7
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
View File

@ -1381,6 +1381,12 @@ static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
}
}
static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
{
if (!adev->gmc.xgmi.connected_to_cpu)
adev->gmc.xgmi.ras = &xgmi_ras;
}
static int gmc_v9_0_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@ -1404,6 +1410,7 @@ static int gmc_v9_0_early_init(void *handle)
gmc_v9_0_set_gfxhub_funcs(adev);
gmc_v9_0_set_hdp_ras_funcs(adev);
gmc_v9_0_set_mca_ras_funcs(adev);
gmc_v9_0_set_xgmi_ras_funcs(adev);
adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
adev->gmc.shared_aperture_end =