bpf/tests: add tests for cpuv4 instructions
The BPF JITs now support cpuv4 instructions. Add tests for these new instructions to the test suite: 1. Sign extended Load 2. Sign extended Mov 3. Unconditional byte swap 4. Unconditional jump with 32-bit offset 5. Signed division and modulo Signed-off-by: Puranjay Mohan <puranjay12@gmail.com> Link: https://lore.kernel.org/r/20230907230550.1417590-9-puranjay12@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
This commit is contained in:
Puranjay Mohan
Alexei Starovoitov
parent
59ff6d63b7
commit
daabb2b098
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@ -117,21 +117,25 @@ struct ctl_table_header;
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/* ALU ops on immediates, bpf_add|sub|...: dst_reg += imm32 */
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#define BPF_ALU64_IMM(OP, DST, IMM) \
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#define BPF_ALU64_IMM_OFF(OP, DST, IMM, OFF) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.off = OFF, \
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.imm = IMM })
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#define BPF_ALU64_IMM(OP, DST, IMM) \
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BPF_ALU64_IMM_OFF(OP, DST, IMM, 0)
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#define BPF_ALU32_IMM(OP, DST, IMM) \
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#define BPF_ALU32_IMM_OFF(OP, DST, IMM, OFF) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_OP(OP) | BPF_K, \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.off = OFF, \
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.imm = IMM })
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#define BPF_ALU32_IMM(OP, DST, IMM) \
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BPF_ALU32_IMM_OFF(OP, DST, IMM, 0)
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/* Endianess conversion, cpu_to_{l,b}e(), {l,b}e_to_cpu() */
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@ -143,6 +147,16 @@ struct ctl_table_header;
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.off = 0, \
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.imm = LEN })
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/* Byte Swap, bswap16/32/64 */
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#define BPF_BSWAP(DST, LEN) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_END | BPF_SRC(BPF_TO_LE), \
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.dst_reg = DST, \
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.src_reg = 0, \
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.off = 0, \
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.imm = LEN })
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/* Short form of mov, dst_reg = src_reg */
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#define BPF_MOV64_REG(DST, SRC) \
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@ -179,6 +193,24 @@ struct ctl_table_header;
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.off = 0, \
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.imm = IMM })
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/* Short form of movsx, dst_reg = (s8,s16,s32)src_reg */
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#define BPF_MOVSX64_REG(DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_ALU64 | BPF_MOV | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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#define BPF_MOVSX32_REG(DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_ALU | BPF_MOV | BPF_X, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Special form of mov32, used for doing explicit zero extension on dst. */
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#define BPF_ZEXT_REG(DST) \
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((struct bpf_insn) { \
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@ -263,6 +295,16 @@ static inline bool insn_is_zext(const struct bpf_insn *insn)
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.off = OFF, \
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.imm = 0 })
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/* Memory load, dst_reg = *(signed size *) (src_reg + off16) */
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#define BPF_LDX_MEMSX(SIZE, DST, SRC, OFF) \
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((struct bpf_insn) { \
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.code = BPF_LDX | BPF_SIZE(SIZE) | BPF_MEMSX, \
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.dst_reg = DST, \
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.src_reg = SRC, \
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.off = OFF, \
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.imm = 0 })
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/* Memory store, *(uint *) (dst_reg + off16) = src_reg */
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#define BPF_STX_MEM(SIZE, DST, SRC, OFF) \
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371
lib/test_bpf.c
371
lib/test_bpf.c
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@ -5111,6 +5111,104 @@ static struct bpf_test tests[] = {
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{ },
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{ { 0, 0xffffffff } }
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},
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/* MOVSX32 */
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{
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"ALU_MOVSX | BPF_B",
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.u.insns_int = {
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BPF_LD_IMM64(R2, 0x00000000ffffffefLL),
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BPF_LD_IMM64(R3, 0xdeadbeefdeadbeefLL),
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BPF_MOVSX32_REG(R1, R3, 8),
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BPF_JMP_REG(BPF_JEQ, R2, R1, 2),
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BPF_MOV32_IMM(R0, 2),
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BPF_EXIT_INSN(),
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BPF_MOV32_IMM(R0, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x1 } },
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},
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{
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"ALU_MOVSX | BPF_H",
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.u.insns_int = {
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BPF_LD_IMM64(R2, 0x00000000ffffbeefLL),
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BPF_LD_IMM64(R3, 0xdeadbeefdeadbeefLL),
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BPF_MOVSX32_REG(R1, R3, 16),
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BPF_JMP_REG(BPF_JEQ, R2, R1, 2),
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BPF_MOV32_IMM(R0, 2),
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BPF_EXIT_INSN(),
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BPF_MOV32_IMM(R0, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x1 } },
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},
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{
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"ALU_MOVSX | BPF_W",
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.u.insns_int = {
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BPF_LD_IMM64(R2, 0x00000000deadbeefLL),
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BPF_LD_IMM64(R3, 0xdeadbeefdeadbeefLL),
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BPF_MOVSX32_REG(R1, R3, 32),
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BPF_JMP_REG(BPF_JEQ, R2, R1, 2),
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BPF_MOV32_IMM(R0, 2),
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BPF_EXIT_INSN(),
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BPF_MOV32_IMM(R0, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x1 } },
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},
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/* MOVSX64 REG */
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{
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"ALU64_MOVSX | BPF_B",
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.u.insns_int = {
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BPF_LD_IMM64(R2, 0xffffffffffffffefLL),
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BPF_LD_IMM64(R3, 0xdeadbeefdeadbeefLL),
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BPF_MOVSX64_REG(R1, R3, 8),
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BPF_JMP_REG(BPF_JEQ, R2, R1, 2),
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BPF_MOV32_IMM(R0, 2),
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BPF_EXIT_INSN(),
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BPF_MOV32_IMM(R0, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x1 } },
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},
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{
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"ALU64_MOVSX | BPF_H",
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.u.insns_int = {
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BPF_LD_IMM64(R2, 0xffffffffffffbeefLL),
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BPF_LD_IMM64(R3, 0xdeadbeefdeadbeefLL),
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BPF_MOVSX64_REG(R1, R3, 16),
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BPF_JMP_REG(BPF_JEQ, R2, R1, 2),
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BPF_MOV32_IMM(R0, 2),
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BPF_EXIT_INSN(),
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BPF_MOV32_IMM(R0, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x1 } },
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},
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{
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"ALU64_MOVSX | BPF_W",
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.u.insns_int = {
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BPF_LD_IMM64(R2, 0xffffffffdeadbeefLL),
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BPF_LD_IMM64(R3, 0xdeadbeefdeadbeefLL),
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BPF_MOVSX64_REG(R1, R3, 32),
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BPF_JMP_REG(BPF_JEQ, R2, R1, 2),
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BPF_MOV32_IMM(R0, 2),
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BPF_EXIT_INSN(),
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BPF_MOV32_IMM(R0, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x1 } },
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},
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/* BPF_ALU | BPF_ADD | BPF_X */
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{
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"ALU_ADD_X: 1 + 2 = 3",
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@ -6105,6 +6203,106 @@ static struct bpf_test tests[] = {
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{ },
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{ { 0, 2 } },
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},
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/* BPF_ALU | BPF_DIV | BPF_X off=1 (SDIV) */
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{
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"ALU_SDIV_X: -6 / 2 = -3",
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.u.insns_int = {
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BPF_LD_IMM64(R0, -6),
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BPF_ALU32_IMM(BPF_MOV, R1, 2),
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BPF_ALU32_REG_OFF(BPF_DIV, R0, R1, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, -3 } },
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},
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/* BPF_ALU | BPF_DIV | BPF_K off=1 (SDIV) */
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{
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"ALU_SDIV_K: -6 / 2 = -3",
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.u.insns_int = {
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BPF_LD_IMM64(R0, -6),
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BPF_ALU32_IMM_OFF(BPF_DIV, R0, 2, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, -3 } },
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},
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/* BPF_ALU64 | BPF_DIV | BPF_X off=1 (SDIV64) */
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{
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"ALU64_SDIV_X: -6 / 2 = -3",
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.u.insns_int = {
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BPF_LD_IMM64(R0, -6),
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BPF_ALU32_IMM(BPF_MOV, R1, 2),
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BPF_ALU64_REG_OFF(BPF_DIV, R0, R1, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, -3 } },
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},
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/* BPF_ALU64 | BPF_DIV | BPF_K off=1 (SDIV64) */
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{
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"ALU64_SDIV_K: -6 / 2 = -3",
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.u.insns_int = {
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BPF_LD_IMM64(R0, -6),
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BPF_ALU64_IMM_OFF(BPF_DIV, R0, 2, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, -3 } },
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},
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/* BPF_ALU | BPF_MOD | BPF_X off=1 (SMOD) */
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{
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"ALU_SMOD_X: -7 % 2 = -1",
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.u.insns_int = {
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BPF_LD_IMM64(R0, -7),
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BPF_ALU32_IMM(BPF_MOV, R1, 2),
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BPF_ALU32_REG_OFF(BPF_MOD, R0, R1, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, -1 } },
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},
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/* BPF_ALU | BPF_MOD | BPF_K off=1 (SMOD) */
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{
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"ALU_SMOD_K: -7 % 2 = -1",
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.u.insns_int = {
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BPF_LD_IMM64(R0, -7),
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BPF_ALU32_IMM_OFF(BPF_MOD, R0, 2, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, -1 } },
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},
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/* BPF_ALU64 | BPF_MOD | BPF_X off=1 (SMOD64) */
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{
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"ALU64_SMOD_X: -7 % 2 = -1",
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.u.insns_int = {
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BPF_LD_IMM64(R0, -7),
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BPF_ALU32_IMM(BPF_MOV, R1, 2),
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BPF_ALU64_REG_OFF(BPF_MOD, R0, R1, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, -1 } },
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},
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/* BPF_ALU64 | BPF_MOD | BPF_K off=1 (SMOD64) */
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{
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"ALU64_SMOD_X: -7 % 2 = -1",
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.u.insns_int = {
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BPF_LD_IMM64(R0, -7),
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BPF_ALU64_IMM_OFF(BPF_MOD, R0, 2, 1),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, -1 } },
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},
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/* BPF_ALU | BPF_AND | BPF_X */
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{
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"ALU_AND_X: 3 & 2 = 2",
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@ -7837,6 +8035,104 @@ static struct bpf_test tests[] = {
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{ },
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{ { 0, (u32) (cpu_to_le64(0xfedcba9876543210ULL) >> 32) } },
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},
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/* BSWAP */
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{
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"BSWAP 16: 0x0123456789abcdef -> 0xefcd",
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.u.insns_int = {
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BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
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BPF_BSWAP(R0, 16),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0xefcd } },
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},
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{
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"BSWAP 32: 0x0123456789abcdef -> 0xefcdab89",
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.u.insns_int = {
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BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
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BPF_BSWAP(R0, 32),
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BPF_ALU64_REG(BPF_MOV, R1, R0),
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BPF_ALU64_IMM(BPF_RSH, R1, 32),
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BPF_ALU32_REG(BPF_ADD, R0, R1), /* R1 = 0 */
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0xefcdab89 } },
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},
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{
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"BSWAP 64: 0x0123456789abcdef -> 0x67452301",
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.u.insns_int = {
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BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
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BPF_BSWAP(R0, 64),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x67452301 } },
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},
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{
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"BSWAP 64: 0x0123456789abcdef >> 32 -> 0xefcdab89",
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.u.insns_int = {
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BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
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BPF_BSWAP(R0, 64),
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BPF_ALU64_IMM(BPF_RSH, R0, 32),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0xefcdab89 } },
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},
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/* BSWAP, reversed */
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{
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"BSWAP 16: 0xfedcba9876543210 -> 0x1032",
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.u.insns_int = {
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BPF_LD_IMM64(R0, 0xfedcba9876543210ULL),
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BPF_BSWAP(R0, 16),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x1032 } },
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},
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{
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"BSWAP 32: 0xfedcba9876543210 -> 0x10325476",
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.u.insns_int = {
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BPF_LD_IMM64(R0, 0xfedcba9876543210ULL),
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BPF_BSWAP(R0, 32),
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BPF_ALU64_REG(BPF_MOV, R1, R0),
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BPF_ALU64_IMM(BPF_RSH, R1, 32),
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BPF_ALU32_REG(BPF_ADD, R0, R1), /* R1 = 0 */
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x10325476 } },
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},
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{
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"BSWAP 64: 0xfedcba9876543210 -> 0x98badcfe",
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.u.insns_int = {
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BPF_LD_IMM64(R0, 0xfedcba9876543210ULL),
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BPF_BSWAP(R0, 64),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x98badcfe } },
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},
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{
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"BSWAP 64: 0xfedcba9876543210 >> 32 -> 0x10325476",
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.u.insns_int = {
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BPF_LD_IMM64(R0, 0xfedcba9876543210ULL),
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BPF_BSWAP(R0, 64),
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BPF_ALU64_IMM(BPF_RSH, R0, 32),
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BPF_EXIT_INSN(),
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},
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INTERNAL,
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{ },
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{ { 0, 0x10325476 } },
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},
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/* BPF_LDX_MEM B/H/W/DW */
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{
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"BPF_LDX_MEM | BPF_B, base",
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@ -8228,6 +8524,67 @@ static struct bpf_test tests[] = {
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{ { 32, 0 } },
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.stack_depth = 0,
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},
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/* BPF_LDX_MEMSX B/H/W */
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{
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"BPF_LDX_MEMSX | BPF_B",
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.u.insns_int = {
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BPF_LD_IMM64(R1, 0xdead0000000000f0ULL),
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BPF_LD_IMM64(R2, 0xfffffffffffffff0ULL),
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BPF_STX_MEM(BPF_DW, R10, R1, -8),
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#ifdef __BIG_ENDIAN
|
||||
BPF_LDX_MEMSX(BPF_B, R0, R10, -1),
|
||||
#else
|
||||
BPF_LDX_MEMSX(BPF_B, R0, R10, -8),
|
||||
#endif
|
||||
BPF_JMP_REG(BPF_JNE, R0, R2, 1),
|
||||
BPF_ALU64_IMM(BPF_MOV, R0, 0),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
INTERNAL,
|
||||
{ },
|
||||
{ { 0, 0 } },
|
||||
.stack_depth = 8,
|
||||
},
|
||||
{
|
||||
"BPF_LDX_MEMSX | BPF_H",
|
||||
.u.insns_int = {
|
||||
BPF_LD_IMM64(R1, 0xdead00000000f123ULL),
|
||||
BPF_LD_IMM64(R2, 0xfffffffffffff123ULL),
|
||||
BPF_STX_MEM(BPF_DW, R10, R1, -8),
|
||||
#ifdef __BIG_ENDIAN
|
||||
BPF_LDX_MEMSX(BPF_H, R0, R10, -2),
|
||||
#else
|
||||
BPF_LDX_MEMSX(BPF_H, R0, R10, -8),
|
||||
#endif
|
||||
BPF_JMP_REG(BPF_JNE, R0, R2, 1),
|
||||
BPF_ALU64_IMM(BPF_MOV, R0, 0),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
INTERNAL,
|
||||
{ },
|
||||
{ { 0, 0 } },
|
||||
.stack_depth = 8,
|
||||
},
|
||||
{
|
||||
"BPF_LDX_MEMSX | BPF_W",
|
||||
.u.insns_int = {
|
||||
BPF_LD_IMM64(R1, 0x00000000deadbeefULL),
|
||||
BPF_LD_IMM64(R2, 0xffffffffdeadbeefULL),
|
||||
BPF_STX_MEM(BPF_DW, R10, R1, -8),
|
||||
#ifdef __BIG_ENDIAN
|
||||
BPF_LDX_MEMSX(BPF_W, R0, R10, -4),
|
||||
#else
|
||||
BPF_LDX_MEMSX(BPF_W, R0, R10, -8),
|
||||
#endif
|
||||
BPF_JMP_REG(BPF_JNE, R0, R2, 1),
|
||||
BPF_ALU64_IMM(BPF_MOV, R0, 0),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
INTERNAL,
|
||||
{ },
|
||||
{ { 0, 0 } },
|
||||
.stack_depth = 8,
|
||||
},
|
||||
/* BPF_STX_MEM B/H/W/DW */
|
||||
{
|
||||
"BPF_STX_MEM | BPF_B",
|
||||
|
|
@ -9474,6 +9831,20 @@ static struct bpf_test tests[] = {
|
|||
{ },
|
||||
{ { 0, 1 } },
|
||||
},
|
||||
/* BPF_JMP32 | BPF_JA */
|
||||
{
|
||||
"JMP32_JA: Unconditional jump: if (true) return 1",
|
||||
.u.insns_int = {
|
||||
BPF_ALU32_IMM(BPF_MOV, R0, 0),
|
||||
BPF_JMP32_IMM(BPF_JA, 0, 1, 0),
|
||||
BPF_EXIT_INSN(),
|
||||
BPF_ALU32_IMM(BPF_MOV, R0, 1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
INTERNAL,
|
||||
{ },
|
||||
{ { 0, 1 } },
|
||||
},
|
||||
/* BPF_JMP | BPF_JSLT | BPF_K */
|
||||
{
|
||||
"JMP_JSLT_K: Signed jump: if (-2 < -1) return 1",
|
||||
|
|
|
|||
Loading…
Reference in New Issue