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scsi: smartpqi: fix critical ARM issue reading PQI index registers
Use the readl() kernel function to read all index registers. For ARM systems, this function includes a read memory barrier that eliminates ci/pi corruption. Reviewed-by: Scott Benesh <scott.benesh@microsemi.com> Reviewed-by: Scott Teel <scott.teel@microsemi.com> Tested-by: Shunyong Yang <shunyong.yang@hxt-semitech.com> Signed-off-by: Kevin Barnett <kevin.barnett@microsemi.com> Signed-off-by: Don Brace <don.brace@microsemi.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
parent
9f8d05fa98
commit
dac12fbc7b
2 changed files with 30 additions and 25 deletions
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@ -583,8 +583,8 @@ struct pqi_admin_queues_aligned {
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struct pqi_admin_queues {
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void *iq_element_array;
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void *oq_element_array;
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volatile pqi_index_t *iq_ci;
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volatile pqi_index_t *oq_pi;
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pqi_index_t *iq_ci;
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pqi_index_t __iomem *oq_pi;
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dma_addr_t iq_element_array_bus_addr;
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dma_addr_t oq_element_array_bus_addr;
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dma_addr_t iq_ci_bus_addr;
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@ -608,8 +608,8 @@ struct pqi_queue_group {
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dma_addr_t oq_element_array_bus_addr;
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__le32 __iomem *iq_pi[2];
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pqi_index_t iq_pi_copy[2];
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volatile pqi_index_t *iq_ci[2];
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volatile pqi_index_t *oq_pi;
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pqi_index_t __iomem *iq_ci[2];
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pqi_index_t __iomem *oq_pi;
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dma_addr_t iq_ci_bus_addr[2];
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dma_addr_t oq_pi_bus_addr;
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__le32 __iomem *oq_ci;
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@ -622,7 +622,7 @@ struct pqi_event_queue {
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u16 oq_id;
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u16 int_msg_num;
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void *oq_element_array;
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volatile pqi_index_t *oq_pi;
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pqi_index_t __iomem *oq_pi;
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dma_addr_t oq_element_array_bus_addr;
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dma_addr_t oq_pi_bus_addr;
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__le32 __iomem *oq_ci;
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@ -2703,7 +2703,7 @@ static unsigned int pqi_process_io_intr(struct pqi_ctrl_info *ctrl_info,
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oq_ci = queue_group->oq_ci_copy;
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while (1) {
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oq_pi = *queue_group->oq_pi;
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oq_pi = readl(queue_group->oq_pi);
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if (oq_pi == oq_ci)
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break;
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@ -2794,7 +2794,7 @@ static void pqi_send_event_ack(struct pqi_ctrl_info *ctrl_info,
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spin_lock_irqsave(&queue_group->submit_lock[RAID_PATH], flags);
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iq_pi = queue_group->iq_pi_copy[RAID_PATH];
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iq_ci = *queue_group->iq_ci[RAID_PATH];
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iq_ci = readl(queue_group->iq_ci[RAID_PATH]);
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if (pqi_num_elements_free(iq_pi, iq_ci,
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ctrl_info->num_elements_per_iq))
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@ -2953,7 +2953,7 @@ static unsigned int pqi_process_event_intr(struct pqi_ctrl_info *ctrl_info)
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oq_ci = event_queue->oq_ci_copy;
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while (1) {
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oq_pi = *event_queue->oq_pi;
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oq_pi = readl(event_queue->oq_pi);
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if (oq_pi == oq_ci)
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break;
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@ -3177,7 +3177,7 @@ static int pqi_alloc_operational_queues(struct pqi_ctrl_info *ctrl_info)
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size_t element_array_length_per_iq;
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size_t element_array_length_per_oq;
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void *element_array;
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void *next_queue_index;
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void __iomem *next_queue_index;
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void *aligned_pointer;
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unsigned int num_inbound_queues;
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unsigned int num_outbound_queues;
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@ -3273,7 +3273,7 @@ static int pqi_alloc_operational_queues(struct pqi_ctrl_info *ctrl_info)
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element_array += PQI_NUM_EVENT_QUEUE_ELEMENTS *
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PQI_EVENT_OQ_ELEMENT_LENGTH;
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next_queue_index = PTR_ALIGN(element_array,
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next_queue_index = (void __iomem *)PTR_ALIGN(element_array,
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PQI_OPERATIONAL_INDEX_ALIGNMENT);
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for (i = 0; i < ctrl_info->num_queue_groups; i++) {
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@ -3281,21 +3281,24 @@ static int pqi_alloc_operational_queues(struct pqi_ctrl_info *ctrl_info)
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queue_group->iq_ci[RAID_PATH] = next_queue_index;
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queue_group->iq_ci_bus_addr[RAID_PATH] =
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ctrl_info->queue_memory_base_dma_handle +
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(next_queue_index - ctrl_info->queue_memory_base);
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(next_queue_index -
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(void __iomem *)ctrl_info->queue_memory_base);
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next_queue_index += sizeof(pqi_index_t);
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next_queue_index = PTR_ALIGN(next_queue_index,
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PQI_OPERATIONAL_INDEX_ALIGNMENT);
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queue_group->iq_ci[AIO_PATH] = next_queue_index;
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queue_group->iq_ci_bus_addr[AIO_PATH] =
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ctrl_info->queue_memory_base_dma_handle +
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(next_queue_index - ctrl_info->queue_memory_base);
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(next_queue_index -
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(void __iomem *)ctrl_info->queue_memory_base);
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next_queue_index += sizeof(pqi_index_t);
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next_queue_index = PTR_ALIGN(next_queue_index,
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PQI_OPERATIONAL_INDEX_ALIGNMENT);
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queue_group->oq_pi = next_queue_index;
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queue_group->oq_pi_bus_addr =
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ctrl_info->queue_memory_base_dma_handle +
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(next_queue_index - ctrl_info->queue_memory_base);
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(next_queue_index -
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(void __iomem *)ctrl_info->queue_memory_base);
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next_queue_index += sizeof(pqi_index_t);
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next_queue_index = PTR_ALIGN(next_queue_index,
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PQI_OPERATIONAL_INDEX_ALIGNMENT);
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@ -3304,7 +3307,8 @@ static int pqi_alloc_operational_queues(struct pqi_ctrl_info *ctrl_info)
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ctrl_info->event_queue.oq_pi = next_queue_index;
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ctrl_info->event_queue.oq_pi_bus_addr =
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ctrl_info->queue_memory_base_dma_handle +
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(next_queue_index - ctrl_info->queue_memory_base);
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(next_queue_index -
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(void __iomem *)ctrl_info->queue_memory_base);
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return 0;
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}
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@ -3378,7 +3382,8 @@ static int pqi_alloc_admin_queues(struct pqi_ctrl_info *ctrl_info)
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admin_queues->oq_element_array =
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&admin_queues_aligned->oq_element_array;
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admin_queues->iq_ci = &admin_queues_aligned->iq_ci;
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admin_queues->oq_pi = &admin_queues_aligned->oq_pi;
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admin_queues->oq_pi =
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(pqi_index_t __iomem *)&admin_queues_aligned->oq_pi;
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admin_queues->iq_element_array_bus_addr =
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ctrl_info->admin_queue_memory_base_dma_handle +
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@ -3394,8 +3399,8 @@ static int pqi_alloc_admin_queues(struct pqi_ctrl_info *ctrl_info)
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ctrl_info->admin_queue_memory_base);
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admin_queues->oq_pi_bus_addr =
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ctrl_info->admin_queue_memory_base_dma_handle +
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((void *)admin_queues->oq_pi -
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ctrl_info->admin_queue_memory_base);
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((void __iomem *)admin_queues->oq_pi -
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(void __iomem *)ctrl_info->admin_queue_memory_base);
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return 0;
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}
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@ -3496,7 +3501,7 @@ static int pqi_poll_for_admin_response(struct pqi_ctrl_info *ctrl_info,
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timeout = (PQI_ADMIN_REQUEST_TIMEOUT_SECS * HZ) + jiffies;
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while (1) {
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oq_pi = *admin_queues->oq_pi;
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oq_pi = readl(admin_queues->oq_pi);
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if (oq_pi != oq_ci)
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break;
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if (time_after(jiffies, timeout)) {
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@ -3555,7 +3560,7 @@ static void pqi_start_io(struct pqi_ctrl_info *ctrl_info,
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DIV_ROUND_UP(iu_length,
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PQI_OPERATIONAL_IQ_ELEMENT_LENGTH);
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iq_ci = *queue_group->iq_ci[path];
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iq_ci = readl(queue_group->iq_ci[path]);
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if (num_elements_needed > pqi_num_elements_free(iq_pi, iq_ci,
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ctrl_info->num_elements_per_iq))
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@ -5054,7 +5059,7 @@ static int pqi_wait_until_inbound_queues_empty(struct pqi_ctrl_info *ctrl_info)
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iq_pi = queue_group->iq_pi_copy[path];
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while (1) {
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iq_ci = *queue_group->iq_ci[path];
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iq_ci = readl(queue_group->iq_ci[path]);
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if (iq_ci == iq_pi)
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break;
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pqi_check_ctrl_health(ctrl_info);
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@ -6243,20 +6248,20 @@ static void pqi_reinit_queues(struct pqi_ctrl_info *ctrl_info)
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admin_queues = &ctrl_info->admin_queues;
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admin_queues->iq_pi_copy = 0;
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admin_queues->oq_ci_copy = 0;
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*admin_queues->oq_pi = 0;
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writel(0, admin_queues->oq_pi);
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for (i = 0; i < ctrl_info->num_queue_groups; i++) {
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ctrl_info->queue_groups[i].iq_pi_copy[RAID_PATH] = 0;
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ctrl_info->queue_groups[i].iq_pi_copy[AIO_PATH] = 0;
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ctrl_info->queue_groups[i].oq_ci_copy = 0;
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*ctrl_info->queue_groups[i].iq_ci[RAID_PATH] = 0;
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*ctrl_info->queue_groups[i].iq_ci[AIO_PATH] = 0;
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*ctrl_info->queue_groups[i].oq_pi = 0;
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writel(0, ctrl_info->queue_groups[i].iq_ci[RAID_PATH]);
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writel(0, ctrl_info->queue_groups[i].iq_ci[AIO_PATH]);
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writel(0, ctrl_info->queue_groups[i].oq_pi);
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}
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event_queue = &ctrl_info->event_queue;
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*event_queue->oq_pi = 0;
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writel(0, event_queue->oq_pi);
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event_queue->oq_ci_copy = 0;
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}
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