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[ARM] Remove MT_DEVICE_IXP2000 and associated definitions
As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
40df2d1d85
commit
db5b716947
10 changed files with 26 additions and 49 deletions
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@ -60,10 +60,9 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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#define MT_DEVICE 0
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#define MT_DEVICE 0
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#define MT_DEVICE_NONSHARED 1
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#define MT_DEVICE_NONSHARED 1
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#define MT_DEVICE_CACHED 2
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#define MT_DEVICE_CACHED 2
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#define MT_DEVICE_IXP2000 3
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#define MT_DEVICE_WC 3
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#define MT_DEVICE_WC 4
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/*
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/*
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* types 5 onwards can be found in asm/mach/map.h and are undefined
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* types 4 onwards can be found in asm/mach/map.h and are undefined
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* for ioremap
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* for ioremap
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*/
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*/
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@ -18,16 +18,15 @@ struct map_desc {
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unsigned int type;
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unsigned int type;
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};
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};
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/* types 0-4 are defined in asm/io.h */
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/* types 0-3 are defined in asm/io.h */
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#define MT_CACHECLEAN 5
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#define MT_CACHECLEAN 4
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#define MT_MINICLEAN 6
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#define MT_MINICLEAN 5
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#define MT_LOW_VECTORS 7
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#define MT_LOW_VECTORS 6
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#define MT_HIGH_VECTORS 8
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#define MT_HIGH_VECTORS 7
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#define MT_MEMORY 9
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#define MT_MEMORY 8
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#define MT_ROM 10
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#define MT_ROM 9
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#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
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#define MT_NONSHARED_DEVICE MT_DEVICE_NONSHARED
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#define MT_IXP2000_DEVICE MT_DEVICE_IXP2000
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#ifdef CONFIG_MMU
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#ifdef CONFIG_MMU
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extern void iotable_init(struct map_desc *, int);
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extern void iotable_init(struct map_desc *, int);
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@ -184,7 +184,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
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#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
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#define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */
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#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
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#define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */
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#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
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#define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */
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#define L_PTE_MT_DEV_IXP2000 (0x0d << 2) /* 1101 */
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#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
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#define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */
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#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
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#define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */
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#define L_PTE_MT_MASK (0x0f << 2)
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#define L_PTE_MT_MASK (0x0f << 2)
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@ -84,64 +84,57 @@ static struct map_desc ixp2000_io_desc[] __initdata = {
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.virtual = IXP2000_CAP_VIRT_BASE,
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.virtual = IXP2000_CAP_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
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.length = IXP2000_CAP_SIZE,
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.length = IXP2000_CAP_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_INTCTL_VIRT_BASE,
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.virtual = IXP2000_INTCTL_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
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.length = IXP2000_INTCTL_SIZE,
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.length = IXP2000_INTCTL_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_PCI_CREG_VIRT_BASE,
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.virtual = IXP2000_PCI_CREG_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
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.length = IXP2000_PCI_CREG_SIZE,
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.length = IXP2000_PCI_CREG_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_PCI_CSR_VIRT_BASE,
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.virtual = IXP2000_PCI_CSR_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
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.length = IXP2000_PCI_CSR_SIZE,
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.length = IXP2000_PCI_CSR_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_MSF_VIRT_BASE,
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.virtual = IXP2000_MSF_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
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.length = IXP2000_MSF_SIZE,
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.length = IXP2000_MSF_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
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.virtual = IXP2000_SCRATCH_RING_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
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.length = IXP2000_SCRATCH_RING_SIZE,
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.length = IXP2000_SCRATCH_RING_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_SRAM0_VIRT_BASE,
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.virtual = IXP2000_SRAM0_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
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.length = IXP2000_SRAM0_SIZE,
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.length = IXP2000_SRAM0_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_PCI_IO_VIRT_BASE,
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.virtual = IXP2000_PCI_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
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.length = IXP2000_PCI_IO_SIZE,
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.length = IXP2000_PCI_IO_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
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.virtual = IXP2000_PCI_CFG0_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
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.length = IXP2000_PCI_CFG0_SIZE,
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.length = IXP2000_PCI_CFG0_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
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.virtual = IXP2000_PCI_CFG1_VIRT_BASE,
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.pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
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.pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
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.length = IXP2000_PCI_CFG1_SIZE,
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.length = IXP2000_PCI_CFG1_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}
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}
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};
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};
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void __init ixp2000_map_io(void)
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void __init ixp2000_map_io(void)
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{
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{
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/*
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* On IXP2400 CPUs we need to use MT_DEVICE_IXP2000 so that
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* XCB=101 (to avoid triggering erratum #66), and given that
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* this mode speeds up I/O accesses and we have write buffer
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* flushes in the right places anyway, it doesn't hurt to use
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* XCB=101 for all IXP2000s.
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*/
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iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
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iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
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/* Set slowport to 8-bit mode. */
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/* Set slowport to 8-bit mode. */
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@ -70,17 +70,17 @@ static struct map_desc enp2611_io_desc[] __initdata = {
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.virtual = ENP2611_CALEB_VIRT_BASE,
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.virtual = ENP2611_CALEB_VIRT_BASE,
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.pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
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.pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
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.length = ENP2611_CALEB_SIZE,
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.length = ENP2611_CALEB_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = ENP2611_PM3386_0_VIRT_BASE,
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.virtual = ENP2611_PM3386_0_VIRT_BASE,
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.pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
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.pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
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.length = ENP2611_PM3386_0_SIZE,
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.length = ENP2611_PM3386_0_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}, {
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}, {
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.virtual = ENP2611_PM3386_1_VIRT_BASE,
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.virtual = ENP2611_PM3386_1_VIRT_BASE,
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.pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
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.pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
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.length = ENP2611_PM3386_1_SIZE,
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.length = ENP2611_PM3386_1_SIZE,
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.type = MT_DEVICE_IXP2000,
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.type = MT_DEVICE,
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}
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}
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};
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};
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@ -41,13 +41,7 @@
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* Most of the registers are clumped in 4K regions spread throughout
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* Most of the registers are clumped in 4K regions spread throughout
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* the 0xc0000000 -> 0xc0100000 address range, but we just map in
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* the 0xc0000000 -> 0xc0100000 address range, but we just map in
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* the whole range using a single 1 MB section instead of small
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* the whole range using a single 1 MB section instead of small
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* 4K pages. This has two advantages for us:
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* 4K pages.
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*
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* 1) We use only one TLB entry for large number of on-chip I/O devices.
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*
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* 2) We can easily set the Section attributes to XCB=101 on the IXP2400
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* as required per erratum #66. We accomplish this by using a
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* new MT_IXP2000_DEVICE memory type with the bits set as required.
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*
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*
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* CAP stands for CSR Access Proxy.
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* CAP stands for CSR Access Proxy.
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*
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*
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@ -204,13 +204,6 @@ static struct mem_type mem_types[] = {
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
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.domain = DOMAIN_IO,
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.domain = DOMAIN_IO,
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},
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},
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[MT_DEVICE_IXP2000] = { /* IXP2400 requires XCB=101 for on-chip I/O */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_IXP2000,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE |
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PMD_SECT_TEX(1),
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.domain = DOMAIN_IO,
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},
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[MT_DEVICE_WC] = { /* ioremap_wc */
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[MT_DEVICE_WC] = { /* ioremap_wc */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_l1 = PMD_TYPE_TABLE,
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@ -119,7 +119,7 @@
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ L_PTE_MT_DEV_IXP2000
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.endm
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.endm
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@ -360,7 +360,7 @@ cpu_xsc3_mt_table:
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ L_PTE_MT_DEV_IXP2000 (not present)
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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@ -443,7 +443,7 @@ cpu_xscale_mt_table:
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long 0x00 @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ L_PTE_MT_DEV_NONSHARED
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.long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_IXP2000
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long 0x00 @ unused
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