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arm64: dts: mt8192: Add mmc device nodes

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In mt8192 SoC, mmc driver dose not use the MSDC module to control
clock. It will read/write register to enable/disable clock. Also
there is no other device of mt8192 using MSDC controller.

We add mmc nodes for mt8192 SoC and remove the clock-controller in
dts for avoid a duplicate unit-address(11f60000) warning.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220407113703.26423-2-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Allen-KH Cheng 2022-04-07 19:37:03 +08:00 committed by Matthias Brugger
parent 71b946e950
commit db61337e49
1 changed files with 30 additions and 4 deletions
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34
arch/arm64/boot/dts/mediatek/mt8192.dtsi
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@ -1123,10 +1123,36 @@ msdc_top: clock-controller@11f10000 {
#clock-cells = <1>;
};
msdc: clock-controller@11f60000 {
compatible = "mediatek,mt8192-msdc";
reg = <0 0x11f60000 0 0x1000>;
#clock-cells = <1>;
mmc0: mmc@11f60000 {
compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
<&msdc_top CLK_MSDC_TOP_H_MST_0P>,
<&msdc_top CLK_MSDC_TOP_SRC_0P>,
<&msdc_top CLK_MSDC_TOP_P_CFG>,
<&msdc_top CLK_MSDC_TOP_P_MSDC0>,
<&msdc_top CLK_MSDC_TOP_AXI>,
<&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
clock-names = "source", "hclk", "source_cg", "sys_cg",
"pclk_cg", "axi_cg", "ahb_cg";
status = "disabled";
};
mmc1: mmc@11f70000 {
compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
<&msdc_top CLK_MSDC_TOP_H_MST_1P>,
<&msdc_top CLK_MSDC_TOP_SRC_1P>,
<&msdc_top CLK_MSDC_TOP_P_CFG>,
<&msdc_top CLK_MSDC_TOP_P_MSDC1>,
<&msdc_top CLK_MSDC_TOP_AXI>,
<&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>;
clock-names = "source", "hclk", "source_cg", "sys_cg",
"pclk_cg", "axi_cg", "ahb_cg";
status = "disabled";
};
mfgcfg: clock-controller@13fbf000 {