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serial: stm32: avoid clearing DMAT bit during transfer
It's rather advised to rely on DMA pause / resume instead of clearing/setting DMA request enable bit for the same purpose. Some DMA request/acknowledge race may encountered by doing so. We prefer to use dmaengine_pause and resume instead to pause a dma transfer when it is necessary. It is also safer to close DMA before reset DMAT in stm32_usart_shutdown. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Link: https://lore.kernel.org/r/20230808161906.178996-2-valentin.caron@foss.st.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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parent
e112ec4202
commit
db89728aba
1 changed files with 44 additions and 32 deletions
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@ -506,13 +506,6 @@ static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
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return stm32_port->tx_dma_busy;
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}
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static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port)
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{
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const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT);
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}
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static void stm32_usart_tx_dma_complete(void *arg)
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{
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struct uart_port *port = arg;
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@ -591,9 +584,6 @@ static void stm32_usart_transmit_chars_pio(struct uart_port *port)
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const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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if (stm32_usart_tx_dma_enabled(stm32_port))
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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while (!uart_circ_empty(xmit)) {
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/* Check that TDR is empty before filling FIFO */
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if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
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@ -616,10 +606,16 @@ static void stm32_usart_transmit_chars_dma(struct uart_port *port)
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struct circ_buf *xmit = &port->state->xmit;
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struct dma_async_tx_descriptor *desc = NULL;
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unsigned int count;
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int ret;
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if (stm32_usart_tx_dma_started(stm32port)) {
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if (!stm32_usart_tx_dma_enabled(stm32port))
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stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
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if (dmaengine_tx_status(stm32port->tx_ch,
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stm32port->tx_ch->cookie,
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NULL) == DMA_PAUSED) {
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ret = dmaengine_resume(stm32port->tx_ch);
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if (ret < 0)
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goto dma_err;
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}
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return;
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}
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@ -664,11 +660,9 @@ static void stm32_usart_transmit_chars_dma(struct uart_port *port)
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desc->callback_param = port;
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/* Push current DMA TX transaction in the pending queue */
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if (dma_submit_error(dmaengine_submit(desc))) {
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/* dma no yet started, safe to free resources */
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stm32_usart_tx_dma_terminate(stm32port);
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goto fallback_err;
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}
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/* DMA no yet started, safe to free resources */
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if (dma_submit_error(dmaengine_submit(desc)))
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goto dma_err;
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/* Issue pending DMA TX requests */
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dma_async_issue_pending(stm32port->tx_ch);
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@ -679,6 +673,10 @@ static void stm32_usart_transmit_chars_dma(struct uart_port *port)
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return;
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dma_err:
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dev_err(port->dev, "DMA failed with error code: %d\n", ret);
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stm32_usart_tx_dma_terminate(stm32port);
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fallback_err:
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stm32_usart_transmit_chars_pio(port);
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}
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@ -701,9 +699,15 @@ static void stm32_usart_transmit_chars(struct uart_port *port)
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if (port->x_char) {
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if (stm32_usart_tx_dma_started(stm32_port) &&
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stm32_usart_tx_dma_enabled(stm32_port))
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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dmaengine_tx_status(stm32_port->tx_ch,
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stm32_port->tx_ch->cookie,
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NULL) == DMA_IN_PROGRESS) {
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ret = dmaengine_pause(stm32_port->tx_ch);
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if (ret < 0) {
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dev_err(port->dev, "DMA failed with error code: %d\n", ret);
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stm32_usart_tx_dma_terminate(stm32_port);
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}
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}
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/* Check that TDR is empty before filling FIFO */
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ret =
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readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
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@ -716,8 +720,14 @@ static void stm32_usart_transmit_chars(struct uart_port *port)
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writel_relaxed(port->x_char, port->membase + ofs->tdr);
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port->x_char = 0;
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port->icount.tx++;
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if (stm32_usart_tx_dma_started(stm32_port))
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stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
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if (stm32_usart_tx_dma_started(stm32_port)) {
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ret = dmaengine_resume(stm32_port->tx_ch);
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if (ret < 0) {
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dev_err(port->dev, "DMA failed with error code: %d\n", ret);
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stm32_usart_tx_dma_terminate(stm32_port);
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}
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}
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return;
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}
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@ -850,11 +860,16 @@ static void stm32_usart_disable_ms(struct uart_port *port)
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static void stm32_usart_stop_tx(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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int ret;
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stm32_usart_tx_interrupt_disable(port);
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if (stm32_usart_tx_dma_started(stm32_port) && stm32_usart_tx_dma_enabled(stm32_port))
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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if (stm32_usart_tx_dma_started(stm32_port)) {
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ret = dmaengine_pause(stm32_port->tx_ch);
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if (ret < 0) {
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dev_err(port->dev, "DMA failed with error code: %d\n", ret);
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stm32_usart_tx_dma_terminate(stm32_port);
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}
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}
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stm32_usart_rs485_rts_disable(port);
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}
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@ -878,12 +893,9 @@ static void stm32_usart_start_tx(struct uart_port *port)
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static void stm32_usart_flush_buffer(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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if (stm32_port->tx_ch) {
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if (stm32_port->tx_ch)
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stm32_usart_tx_dma_terminate(stm32_port);
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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}
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}
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/* Throttle the remote when input buffer is about to overflow. */
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@ -1042,12 +1054,12 @@ static void stm32_usart_shutdown(struct uart_port *port)
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u32 val, isr;
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int ret;
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if (stm32_usart_tx_dma_enabled(stm32_port))
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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if (stm32_usart_tx_dma_started(stm32_port))
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stm32_usart_tx_dma_terminate(stm32_port);
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if (stm32_port->tx_ch)
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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/* Disable modem control interrupts */
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stm32_usart_disable_ms(port);
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