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ASoC: atmel_ssc_dai: rework DAI format configuration
Rework DAI format calculation in preparation for adding more formats later. As a side-effect this enables all CBM/CBS x CFM/CFS combinations for supported formats. (Note: the additional modes are not tested.) Note: this changes FSEDGE to POSITIVE for I2S CBM_CFS mode as the TXSYN interrupt is not used anyway. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/f5949b0326fdcdca072f3ed03f77de9e207631cd.1566677788.git.mirq-linux@rere.qmqm.pl Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Michał Mirosław
Mark Brown
parent
1829141055
commit
db8e3e2091
1 changed files with 86 additions and 212 deletions
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@ -471,7 +471,7 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
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int dir, channels, bits;
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u32 tfmr, rfmr, tcmr, rcmr;
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int ret;
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int fslen, fslen_ext;
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int fslen, fslen_ext, fs_osync, fs_edge;
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u32 cmr_div;
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u32 tcmr_period;
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u32 rcmr_period;
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@ -558,226 +558,36 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
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/*
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* Compute SSC register settings.
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*/
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switch (ssc_p->daifmt
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& (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
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case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
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fslen_ext = (bits - 1) / 16;
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fslen = (bits - 1) % 16;
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switch (ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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fs_osync = SSC_FSOS_NEGATIVE;
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fs_edge = SSC_START_FALLING_RF;
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rcmr = SSC_BF(RCMR_STTDLY, 1);
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tcmr = SSC_BF(TCMR_STTDLY, 1);
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break;
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case SND_SOC_DAIFMT_DSP_A:
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/*
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* I2S format, SSC provides BCLK and LRC clocks.
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*
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* The SSC transmit and receive clocks are generated
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* from the MCK divider, and the BCLK signal
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* is output on the SSC TK line.
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*/
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if (bits > 16 && !ssc->pdata->has_fslen_ext) {
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dev_err(dai->dev,
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"sample size %d is too large for SSC device\n",
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bits);
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return -EINVAL;
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}
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fslen_ext = (bits - 1) / 16;
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fslen = (bits - 1) % 16;
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rcmr = SSC_BF(RCMR_PERIOD, rcmr_period)
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| SSC_BF(RCMR_STTDLY, START_DELAY)
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| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
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| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
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rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
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| SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
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| SSC_BF(RFMR_FSLEN, fslen)
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| SSC_BF(RFMR_DATNB, (channels - 1))
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| SSC_BIT(RFMR_MSBF)
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| SSC_BF(RFMR_LOOP, 0)
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| SSC_BF(RFMR_DATLEN, (bits - 1));
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tcmr = SSC_BF(TCMR_PERIOD, tcmr_period)
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| SSC_BF(TCMR_STTDLY, START_DELAY)
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| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
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| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
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| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
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| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
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tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
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| SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(TFMR_FSDEN, 0)
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| SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
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| SSC_BF(TFMR_FSLEN, fslen)
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| SSC_BF(TFMR_DATNB, (channels - 1))
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| SSC_BIT(TFMR_MSBF)
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| SSC_BF(TFMR_DATDEF, 0)
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| SSC_BF(TFMR_DATLEN, (bits - 1));
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break;
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case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
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/* I2S format, CODEC supplies BCLK and LRC clocks. */
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rcmr = SSC_BF(RCMR_PERIOD, 0)
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| SSC_BF(RCMR_STTDLY, START_DELAY)
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| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
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| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
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SSC_CKS_PIN : SSC_CKS_CLOCK);
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rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
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| SSC_BF(RFMR_FSLEN, 0)
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| SSC_BF(RFMR_DATNB, (channels - 1))
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| SSC_BIT(RFMR_MSBF)
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| SSC_BF(RFMR_LOOP, 0)
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| SSC_BF(RFMR_DATLEN, (bits - 1));
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tcmr = SSC_BF(TCMR_PERIOD, 0)
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| SSC_BF(TCMR_STTDLY, START_DELAY)
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| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
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| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
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| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
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SSC_CKS_CLOCK : SSC_CKS_PIN);
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tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(TFMR_FSDEN, 0)
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| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
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| SSC_BF(TFMR_FSLEN, 0)
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| SSC_BF(TFMR_DATNB, (channels - 1))
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| SSC_BIT(TFMR_MSBF)
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| SSC_BF(TFMR_DATDEF, 0)
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| SSC_BF(TFMR_DATLEN, (bits - 1));
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break;
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case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
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/* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
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if (bits > 16 && !ssc->pdata->has_fslen_ext) {
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dev_err(dai->dev,
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"sample size %d is too large for SSC device\n",
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bits);
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return -EINVAL;
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}
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fslen_ext = (bits - 1) / 16;
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fslen = (bits - 1) % 16;
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rcmr = SSC_BF(RCMR_PERIOD, rcmr_period)
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| SSC_BF(RCMR_STTDLY, START_DELAY)
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| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
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| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
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SSC_CKS_PIN : SSC_CKS_CLOCK);
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rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
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| SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
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| SSC_BF(RFMR_FSLEN, fslen)
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| SSC_BF(RFMR_DATNB, (channels - 1))
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| SSC_BIT(RFMR_MSBF)
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| SSC_BF(RFMR_LOOP, 0)
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| SSC_BF(RFMR_DATLEN, (bits - 1));
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tcmr = SSC_BF(TCMR_PERIOD, tcmr_period)
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| SSC_BF(TCMR_STTDLY, START_DELAY)
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| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
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| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
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| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
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SSC_CKS_CLOCK : SSC_CKS_PIN);
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tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
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| SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
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| SSC_BF(TFMR_FSDEN, 0)
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| SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
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| SSC_BF(TFMR_FSLEN, fslen)
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| SSC_BF(TFMR_DATNB, (channels - 1))
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| SSC_BIT(TFMR_MSBF)
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| SSC_BF(TFMR_DATDEF, 0)
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| SSC_BF(TFMR_DATLEN, (bits - 1));
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break;
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case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
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/*
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* DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
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*
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* The SSC transmit and receive clocks are generated from the
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* MCK divider, and the BCLK signal is output
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* on the SSC TK line.
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*/
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rcmr = SSC_BF(RCMR_PERIOD, rcmr_period)
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| SSC_BF(RCMR_STTDLY, 1)
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| SSC_BF(RCMR_START, SSC_START_RISING_RF)
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| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
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rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
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| SSC_BF(RFMR_FSLEN, 0)
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| SSC_BF(RFMR_DATNB, (channels - 1))
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| SSC_BIT(RFMR_MSBF)
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| SSC_BF(RFMR_LOOP, 0)
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| SSC_BF(RFMR_DATLEN, (bits - 1));
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tcmr = SSC_BF(TCMR_PERIOD, tcmr_period)
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| SSC_BF(TCMR_STTDLY, 1)
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| SSC_BF(TCMR_START, SSC_START_RISING_RF)
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| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
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| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
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| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
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tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(TFMR_FSDEN, 0)
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| SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
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| SSC_BF(TFMR_FSLEN, 0)
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| SSC_BF(TFMR_DATNB, (channels - 1))
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| SSC_BIT(TFMR_MSBF)
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| SSC_BF(TFMR_DATDEF, 0)
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| SSC_BF(TFMR_DATLEN, (bits - 1));
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break;
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case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
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/*
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* DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
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* DSP/PCM Mode A format
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*
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* Data is transferred on first BCLK after LRC pulse rising
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* edge.If stereo, the right channel data is contiguous with
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* the left channel data.
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*/
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rcmr = SSC_BF(RCMR_PERIOD, 0)
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| SSC_BF(RCMR_STTDLY, START_DELAY)
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| SSC_BF(RCMR_START, SSC_START_RISING_RF)
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| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
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SSC_CKS_PIN : SSC_CKS_CLOCK);
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fs_osync = SSC_FSOS_POSITIVE;
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fs_edge = SSC_START_RISING_RF;
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fslen = fslen_ext = 0;
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rfmr = SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
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| SSC_BF(RFMR_FSLEN, 0)
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| SSC_BF(RFMR_DATNB, (channels - 1))
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| SSC_BIT(RFMR_MSBF)
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| SSC_BF(RFMR_LOOP, 0)
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| SSC_BF(RFMR_DATLEN, (bits - 1));
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rcmr = SSC_BF(RCMR_STTDLY, 1);
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tcmr = SSC_BF(TCMR_STTDLY, 1);
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tcmr = SSC_BF(TCMR_PERIOD, 0)
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| SSC_BF(TCMR_STTDLY, START_DELAY)
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| SSC_BF(TCMR_START, SSC_START_RISING_RF)
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| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
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| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
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| SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
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SSC_CKS_CLOCK : SSC_CKS_PIN);
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tfmr = SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(TFMR_FSDEN, 0)
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| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
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| SSC_BF(TFMR_FSLEN, 0)
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| SSC_BF(TFMR_DATNB, (channels - 1))
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| SSC_BIT(TFMR_MSBF)
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| SSC_BF(TFMR_DATDEF, 0)
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| SSC_BF(TFMR_DATLEN, (bits - 1));
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break;
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default:
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@ -785,6 +595,70 @@ static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
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ssc_p->daifmt);
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return -EINVAL;
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}
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if (!atmel_ssc_cfs(ssc_p)) {
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fslen = fslen_ext = 0;
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rcmr_period = tcmr_period = 0;
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fs_osync = SSC_FSOS_NONE;
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}
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rcmr |= SSC_BF(RCMR_START, fs_edge);
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tcmr |= SSC_BF(TCMR_START, fs_edge);
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if (atmel_ssc_cbs(ssc_p)) {
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/*
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* SSC provides BCLK
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*
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* The SSC transmit and receive clocks are generated from the
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* MCK divider, and the BCLK signal is output
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* on the SSC TK line.
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*/
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rcmr |= SSC_BF(RCMR_CKS, SSC_CKS_DIV)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE);
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tcmr |= SSC_BF(TCMR_CKS, SSC_CKS_DIV)
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| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS);
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} else {
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rcmr |= SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
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SSC_CKS_PIN : SSC_CKS_CLOCK)
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| SSC_BF(RCMR_CKO, SSC_CKO_NONE);
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tcmr |= SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
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SSC_CKS_CLOCK : SSC_CKS_PIN)
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| SSC_BF(TCMR_CKO, SSC_CKO_NONE);
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}
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rcmr |= SSC_BF(RCMR_PERIOD, rcmr_period)
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| SSC_BF(RCMR_CKI, SSC_CKI_RISING);
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tcmr |= SSC_BF(TCMR_PERIOD, tcmr_period)
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| SSC_BF(TCMR_CKI, SSC_CKI_FALLING);
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rfmr = SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
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| SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(RFMR_FSOS, fs_osync)
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| SSC_BF(RFMR_FSLEN, fslen)
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| SSC_BF(RFMR_DATNB, (channels - 1))
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| SSC_BIT(RFMR_MSBF)
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| SSC_BF(RFMR_LOOP, 0)
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| SSC_BF(RFMR_DATLEN, (bits - 1));
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tfmr = SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
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| SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
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| SSC_BF(TFMR_FSDEN, 0)
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| SSC_BF(TFMR_FSOS, fs_osync)
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| SSC_BF(TFMR_FSLEN, fslen)
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| SSC_BF(TFMR_DATNB, (channels - 1))
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| SSC_BIT(TFMR_MSBF)
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| SSC_BF(TFMR_DATDEF, 0)
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| SSC_BF(TFMR_DATLEN, (bits - 1));
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if (fslen_ext && !ssc->pdata->has_fslen_ext) {
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dev_err(dai->dev, "sample size %d is too large for SSC device\n",
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bits);
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return -EINVAL;
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}
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pr_debug("atmel_ssc_hw_params: "
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"RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
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rcmr, rfmr, tcmr, tfmr);
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