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drm/amd/display: Drop SOC bounding box hookup in DM/DC
[Why] There aren't any ASIC where we use these binaries and they aren't useful for future use since it's inconvenient to extend and maintain these structures. [How] Drop the support from DM and DC for now. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
dd017d01c3
commit
dbb7898ac1
6 changed files with 4 additions and 330 deletions
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@ -1015,8 +1015,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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init_data.flags.power_down_display_on_boot = true;
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init_data.soc_bounding_box = adev->dm.soc_bounding_box;
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/* Display Core create. */
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adev->dm.dc = dc_create(&init_data);
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@ -712,7 +712,6 @@ static bool dc_construct(struct dc *dc,
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}
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dc->dcn_ip = dcn_ip;
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dc->soc_bounding_box = init_params->soc_bounding_box;
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#endif
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if (!dc_construct_ctx(dc, init_params)) {
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@ -638,7 +638,6 @@ struct dc {
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const char *build_id;
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struct vm_helper *vm_helper;
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const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
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};
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enum frame_buffer_mode {
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@ -676,11 +675,6 @@ struct dc_init_data {
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struct dc_config flags;
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uint64_t log_mask;
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/**
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* gpu_info FW provided soc bounding box struct or 0 if not
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* available in FW
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*/
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const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
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struct dpcd_vendor_signature vendor_signature;
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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bool force_smu_not_present;
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@ -3606,7 +3606,6 @@ static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
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static bool init_soc_bounding_box(struct dc *dc,
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struct dcn20_resource_pool *pool)
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{
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const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
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struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
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get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
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struct _vcs_dpi_ip_params_st *loaded_ip =
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@ -3614,116 +3613,6 @@ static bool init_soc_bounding_box(struct dc *dc,
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DC_LOGGER_INIT(dc->ctx->logger);
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/* TODO: upstream NV12 bounding box when its launched */
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if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
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DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
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return false;
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}
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if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
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int i;
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dcn2_0_nv12_soc.sr_exit_time_us =
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fixed16_to_double_to_cpu(bb->sr_exit_time_us);
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dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
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fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
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dcn2_0_nv12_soc.urgent_latency_us =
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fixed16_to_double_to_cpu(bb->urgent_latency_us);
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dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
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fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
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dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
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fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
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dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
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fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
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dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
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le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
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dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
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le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
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dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
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le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
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dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
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fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
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dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
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fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
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dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
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fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
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dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
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fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
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dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
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fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
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dcn2_0_nv12_soc.writeback_latency_us =
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fixed16_to_double_to_cpu(bb->writeback_latency_us);
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dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
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fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
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dcn2_0_nv12_soc.max_request_size_bytes =
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le32_to_cpu(bb->max_request_size_bytes);
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dcn2_0_nv12_soc.dram_channel_width_bytes =
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le32_to_cpu(bb->dram_channel_width_bytes);
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dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
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le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
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dcn2_0_nv12_soc.dcn_downspread_percent =
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fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
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dcn2_0_nv12_soc.downspread_percent =
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fixed16_to_double_to_cpu(bb->downspread_percent);
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dcn2_0_nv12_soc.dram_page_open_time_ns =
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fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
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dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
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fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
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dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
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le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
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dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
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le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
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dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
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le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
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dcn2_0_nv12_soc.channel_interleave_bytes =
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le32_to_cpu(bb->channel_interleave_bytes);
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dcn2_0_nv12_soc.num_banks =
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le32_to_cpu(bb->num_banks);
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dcn2_0_nv12_soc.num_chans =
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le32_to_cpu(bb->num_chans);
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dcn2_0_nv12_soc.vmm_page_size_bytes =
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le32_to_cpu(bb->vmm_page_size_bytes);
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dcn2_0_nv12_soc.dram_clock_change_latency_us =
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fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
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// HACK!! Lower uclock latency switch time so we don't switch
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dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
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dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
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fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
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dcn2_0_nv12_soc.return_bus_width_bytes =
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le32_to_cpu(bb->return_bus_width_bytes);
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dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
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le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
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dcn2_0_nv12_soc.xfc_bus_transport_time_us =
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le32_to_cpu(bb->xfc_bus_transport_time_us);
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dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
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le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
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dcn2_0_nv12_soc.use_urgent_burst_bw =
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le32_to_cpu(bb->use_urgent_burst_bw);
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dcn2_0_nv12_soc.num_states =
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le32_to_cpu(bb->num_states);
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for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
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dcn2_0_nv12_soc.clock_limits[i].state =
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le32_to_cpu(bb->clock_limits[i].state);
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dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
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dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
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dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
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dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
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dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
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dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
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dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
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dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
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}
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}
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if (pool->base.pp_smu) {
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struct pp_smu_nv_clock_table max_clocks = {0};
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unsigned int uclk_states[8] = {0};
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@ -1716,125 +1716,22 @@ static bool is_soc_bounding_box_valid(struct dc *dc)
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static bool init_soc_bounding_box(struct dc *dc,
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struct dcn30_resource_pool *pool)
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{
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const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
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struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
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struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
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DC_LOGGER_INIT(dc->ctx->logger);
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if (!bb && !is_soc_bounding_box_valid(dc)) {
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if (!is_soc_bounding_box_valid(dc)) {
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DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
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return false;
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}
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if (bb && !is_soc_bounding_box_valid(dc)) {
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int i;
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dcn3_0_soc.sr_exit_time_us =
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fixed16_to_double_to_cpu(bb->sr_exit_time_us);
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dcn3_0_soc.sr_enter_plus_exit_time_us =
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fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
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dcn3_0_soc.urgent_latency_us =
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fixed16_to_double_to_cpu(bb->urgent_latency_us);
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dcn3_0_soc.urgent_latency_pixel_data_only_us =
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fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
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dcn3_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
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fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
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dcn3_0_soc.urgent_latency_vm_data_only_us =
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fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
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dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
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le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
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dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
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le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
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dcn3_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
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le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
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dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
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fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
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dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
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fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
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dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
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fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
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dcn3_0_soc.max_avg_sdp_bw_use_normal_percent =
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fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
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dcn3_0_soc.max_avg_dram_bw_use_normal_percent =
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fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
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dcn3_0_soc.writeback_latency_us =
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fixed16_to_double_to_cpu(bb->writeback_latency_us);
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dcn3_0_soc.ideal_dram_bw_after_urgent_percent =
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fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
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dcn3_0_soc.max_request_size_bytes =
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le32_to_cpu(bb->max_request_size_bytes);
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dcn3_0_soc.dram_channel_width_bytes =
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le32_to_cpu(bb->dram_channel_width_bytes);
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dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes =
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le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
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dcn3_0_soc.dcn_downspread_percent =
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fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
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dcn3_0_soc.downspread_percent =
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fixed16_to_double_to_cpu(bb->downspread_percent);
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dcn3_0_soc.dram_page_open_time_ns =
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fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
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dcn3_0_soc.dram_rw_turnaround_time_ns =
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fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
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dcn3_0_soc.dram_return_buffer_per_channel_bytes =
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le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
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dcn3_0_soc.round_trip_ping_latency_dcfclk_cycles =
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le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
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dcn3_0_soc.urgent_out_of_order_return_per_channel_bytes =
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le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
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dcn3_0_soc.channel_interleave_bytes =
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le32_to_cpu(bb->channel_interleave_bytes);
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dcn3_0_soc.num_banks =
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le32_to_cpu(bb->num_banks);
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dcn3_0_soc.num_chans =
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le32_to_cpu(bb->num_chans);
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dcn3_0_soc.gpuvm_min_page_size_bytes =
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le32_to_cpu(bb->vmm_page_size_bytes);
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dcn3_0_soc.dram_clock_change_latency_us =
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fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
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dcn3_0_soc.writeback_dram_clock_change_latency_us =
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fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
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dcn3_0_soc.return_bus_width_bytes =
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le32_to_cpu(bb->return_bus_width_bytes);
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dcn3_0_soc.dispclk_dppclk_vco_speed_mhz =
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le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
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dcn3_0_soc.xfc_bus_transport_time_us =
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le32_to_cpu(bb->xfc_bus_transport_time_us);
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dcn3_0_soc.xfc_xbuf_latency_tolerance_us =
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le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
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dcn3_0_soc.use_urgent_burst_bw =
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le32_to_cpu(bb->use_urgent_burst_bw);
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dcn3_0_soc.num_states =
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le32_to_cpu(bb->num_states);
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for (i = 0; i < dcn3_0_soc.num_states; i++) {
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dcn3_0_soc.clock_limits[i].state =
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le32_to_cpu(bb->clock_limits[i].state);
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dcn3_0_soc.clock_limits[i].dcfclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
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dcn3_0_soc.clock_limits[i].fabricclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
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dcn3_0_soc.clock_limits[i].dispclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
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dcn3_0_soc.clock_limits[i].dppclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
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dcn3_0_soc.clock_limits[i].phyclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
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dcn3_0_soc.clock_limits[i].socclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
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dcn3_0_soc.clock_limits[i].dscclk_mhz =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
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dcn3_0_soc.clock_limits[i].dram_speed_mts =
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fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
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}
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}
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||||
loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
|
||||
loaded_ip->max_num_dpp = pool->base.pipe_count;
|
||||
loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
|
||||
dcn20_patch_bounding_box(dc, loaded_bb);
|
||||
|
||||
if (!bb && dc->ctx->dc_bios->funcs->get_soc_bb_info) {
|
||||
if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
|
||||
struct bp_soc_bb_info bb_info = {0};
|
||||
|
||||
if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
|
||||
|
|
|
@ -1489,124 +1489,21 @@ static bool is_soc_bounding_box_valid(struct dc *dc)
|
|||
static bool init_soc_bounding_box(struct dc *dc,
|
||||
struct dcn301_resource_pool *pool)
|
||||
{
|
||||
const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
|
||||
struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
|
||||
struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
|
||||
|
||||
DC_LOGGER_INIT(dc->ctx->logger);
|
||||
|
||||
if (!bb && !is_soc_bounding_box_valid(dc)) {
|
||||
if (!is_soc_bounding_box_valid(dc)) {
|
||||
DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
|
||||
return false;
|
||||
}
|
||||
|
||||
if (bb && !is_soc_bounding_box_valid(dc)) {
|
||||
int i;
|
||||
|
||||
dcn3_01_soc.sr_exit_time_us =
|
||||
fixed16_to_double_to_cpu(bb->sr_exit_time_us);
|
||||
dcn3_01_soc.sr_enter_plus_exit_time_us =
|
||||
fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
|
||||
dcn3_01_soc.urgent_latency_us =
|
||||
fixed16_to_double_to_cpu(bb->urgent_latency_us);
|
||||
dcn3_01_soc.urgent_latency_pixel_data_only_us =
|
||||
fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
|
||||
dcn3_01_soc.urgent_latency_pixel_mixed_with_vm_data_us =
|
||||
fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
|
||||
dcn3_01_soc.urgent_latency_vm_data_only_us =
|
||||
fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
|
||||
dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
|
||||
le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
|
||||
dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
|
||||
le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
|
||||
dcn3_01_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
|
||||
le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
|
||||
dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
|
||||
fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
|
||||
dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
|
||||
fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
|
||||
dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
|
||||
fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
|
||||
dcn3_01_soc.max_avg_sdp_bw_use_normal_percent =
|
||||
fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
|
||||
dcn3_01_soc.max_avg_dram_bw_use_normal_percent =
|
||||
fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
|
||||
dcn3_01_soc.writeback_latency_us =
|
||||
fixed16_to_double_to_cpu(bb->writeback_latency_us);
|
||||
dcn3_01_soc.ideal_dram_bw_after_urgent_percent =
|
||||
fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
|
||||
dcn3_01_soc.max_request_size_bytes =
|
||||
le32_to_cpu(bb->max_request_size_bytes);
|
||||
dcn3_01_soc.dram_channel_width_bytes =
|
||||
le32_to_cpu(bb->dram_channel_width_bytes);
|
||||
dcn3_01_soc.fabric_datapath_to_dcn_data_return_bytes =
|
||||
le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
|
||||
dcn3_01_soc.dcn_downspread_percent =
|
||||
fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
|
||||
dcn3_01_soc.downspread_percent =
|
||||
fixed16_to_double_to_cpu(bb->downspread_percent);
|
||||
dcn3_01_soc.dram_page_open_time_ns =
|
||||
fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
|
||||
dcn3_01_soc.dram_rw_turnaround_time_ns =
|
||||
fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
|
||||
dcn3_01_soc.dram_return_buffer_per_channel_bytes =
|
||||
le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
|
||||
dcn3_01_soc.round_trip_ping_latency_dcfclk_cycles =
|
||||
le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
|
||||
dcn3_01_soc.urgent_out_of_order_return_per_channel_bytes =
|
||||
le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
|
||||
dcn3_01_soc.channel_interleave_bytes =
|
||||
le32_to_cpu(bb->channel_interleave_bytes);
|
||||
dcn3_01_soc.num_banks =
|
||||
le32_to_cpu(bb->num_banks);
|
||||
dcn3_01_soc.num_chans =
|
||||
le32_to_cpu(bb->num_chans);
|
||||
dcn3_01_soc.gpuvm_min_page_size_bytes =
|
||||
le32_to_cpu(bb->vmm_page_size_bytes);
|
||||
dcn3_01_soc.dram_clock_change_latency_us =
|
||||
fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
|
||||
dcn3_01_soc.writeback_dram_clock_change_latency_us =
|
||||
fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
|
||||
dcn3_01_soc.return_bus_width_bytes =
|
||||
le32_to_cpu(bb->return_bus_width_bytes);
|
||||
dcn3_01_soc.dispclk_dppclk_vco_speed_mhz =
|
||||
le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
|
||||
dcn3_01_soc.xfc_bus_transport_time_us =
|
||||
le32_to_cpu(bb->xfc_bus_transport_time_us);
|
||||
dcn3_01_soc.xfc_xbuf_latency_tolerance_us =
|
||||
le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
|
||||
dcn3_01_soc.use_urgent_burst_bw =
|
||||
le32_to_cpu(bb->use_urgent_burst_bw);
|
||||
dcn3_01_soc.num_states =
|
||||
le32_to_cpu(bb->num_states);
|
||||
|
||||
for (i = 0; i < dcn3_01_soc.num_states; i++) {
|
||||
dcn3_01_soc.clock_limits[i].state =
|
||||
le32_to_cpu(bb->clock_limits[i].state);
|
||||
dcn3_01_soc.clock_limits[i].dcfclk_mhz =
|
||||
fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
|
||||
dcn3_01_soc.clock_limits[i].fabricclk_mhz =
|
||||
fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
|
||||
dcn3_01_soc.clock_limits[i].dispclk_mhz =
|
||||
fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
|
||||
dcn3_01_soc.clock_limits[i].dppclk_mhz =
|
||||
fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
|
||||
dcn3_01_soc.clock_limits[i].phyclk_mhz =
|
||||
fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
|
||||
dcn3_01_soc.clock_limits[i].socclk_mhz =
|
||||
fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
|
||||
dcn3_01_soc.clock_limits[i].dscclk_mhz =
|
||||
fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
|
||||
dcn3_01_soc.clock_limits[i].dram_speed_mts =
|
||||
fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
|
||||
}
|
||||
}
|
||||
|
||||
loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
|
||||
loaded_ip->max_num_dpp = pool->base.pipe_count;
|
||||
dcn20_patch_bounding_box(dc, loaded_bb);
|
||||
|
||||
if (!bb && dc->ctx->dc_bios->funcs->get_soc_bb_info) {
|
||||
if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
|
||||
struct bp_soc_bb_info bb_info = {0};
|
||||
|
||||
if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
|
||||
|
|
Loading…
Reference in a new issue