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pinctrl: renesas: Updates for v5.12
- Restrict debug runtime-checks to Renesas platforms, - Initial support for the R-Car V3U SoC. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYAFgRQAKCRCKwlD9ZEnx cEWIAP40TrUerqfnQgJ7iNYLh9WfSk48w9Gxzm92E7FanXaJBAD/dmkieXwQBBig zKNuoWL2ZlK7O5MMkzpNnhLNS95SEQs= =vIxg -----END PGP SIGNATURE----- Merge tag 'renesas-pinctrl-for-v5.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.12 - Restrict debug runtime-checks to Renesas platforms, - Initial support for the R-Car V3U SoC.
This commit is contained in:
Linus Walleij
commit
dbbdb8da42
7 changed files with 4533 additions and 18 deletions
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@ -43,11 +43,12 @@ properties:
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- renesas,pfc-r8a77980 # R-Car V3H
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- renesas,pfc-r8a77990 # R-Car E3
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- renesas,pfc-r8a77995 # R-Car D3
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- renesas,pfc-r8a779a0 # R-Car V3U
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- renesas,pfc-sh73a0 # SH-Mobile AG5
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reg:
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minItems: 1
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maxItems: 2
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maxItems: 10
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gpio-controller: true
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@ -36,6 +36,7 @@ config PINCTRL_RENESAS
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select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
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select PINCTRL_PFC_R8A77990 if ARCH_R8A77990
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select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
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select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
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select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
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select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
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select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
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@ -142,6 +143,10 @@ config PINCTRL_PFC_R8A77970
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bool "pin control support for R-Car V3M" if COMPILE_TEST
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A779A0
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bool "pin control support for R-Car V3U" if COMPILE_TEST
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A7740
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bool "pin control support for R-Mobile A1" if COMPILE_TEST
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select PINCTRL_SH_PFC_GPIO
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@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
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obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
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obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
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obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
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obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
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obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
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@ -175,13 +175,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
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return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
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}
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static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
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{
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u32 unlock;
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if (!pfc->info->unlock_reg)
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return;
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if (pfc->info->unlock_reg >= 0x80000000UL)
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unlock = pfc->info->unlock_reg;
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else
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/* unlock_reg is a mask */
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unlock = reg & ~pfc->info->unlock_reg;
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sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
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}
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void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
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{
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(
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sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
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~data);
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sh_pfc_unlock_reg(pfc, reg, data);
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sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
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}
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@ -227,11 +239,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
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data &= mask;
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data |= value;
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if (pfc->info->unlock_reg)
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sh_pfc_write_raw_reg(
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sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
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~data);
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sh_pfc_unlock_reg(pfc, crp->reg, data);
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sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
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}
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@ -638,6 +646,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
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.data = &r8a77995_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A779A0
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{
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.compatible = "renesas,pfc-r8a779a0",
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.data = &r8a779a0_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_SH73A0
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{
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.compatible = "renesas,pfc-sh73a0",
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@ -1052,6 +1066,10 @@ static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
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{
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unsigned int i;
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if (!IS_ENABLED(CONFIG_SUPERH) &&
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!of_find_matching_node(NULL, pdrv->driver.of_match_table))
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return;
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sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
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GFP_KERNEL);
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if (!sh_pfc_regs)
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4460
drivers/pinctrl/renesas/pfc-r8a779a0.c
Normal file
4460
drivers/pinctrl/renesas/pfc-r8a779a0.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -634,6 +634,9 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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}
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case PIN_CONFIG_POWER_SOURCE: {
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int idx = sh_pfc_get_pin_index(pfc, _pin);
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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unsigned int lower_voltage;
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u32 pocctrl, val;
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int bit;
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@ -648,7 +651,10 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
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val = sh_pfc_read(pfc, pocctrl);
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spin_unlock_irqrestore(&pfc->lock, flags);
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arg = (val & BIT(bit)) ? 3300 : 1800;
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lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
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2500 : 1800;
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arg = (val & BIT(bit)) ? 3300 : lower_voltage;
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break;
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}
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@ -702,6 +708,9 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
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case PIN_CONFIG_POWER_SOURCE: {
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unsigned int mV = pinconf_to_config_argument(configs[i]);
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int idx = sh_pfc_get_pin_index(pfc, _pin);
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const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
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unsigned int lower_voltage;
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u32 pocctrl, val;
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int bit;
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@ -712,7 +721,10 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
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if (WARN(bit < 0, "invalid pin %#x", _pin))
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return bit;
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if (mV != 1800 && mV != 3300)
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lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
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2500 : 1800;
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if (mV != lower_voltage && mV != 3300)
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return -EINVAL;
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spin_lock_irqsave(&pfc->lock, flags);
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@ -31,6 +31,15 @@ enum {
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SH_PFC_PIN_CFG_PULL_DOWN)
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#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
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#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
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#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
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#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
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#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
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SH_PFC_PIN_VOLTAGE_18_33)
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#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
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SH_PFC_PIN_VOLTAGE_25_33)
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#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
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struct sh_pfc_pin {
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@ -300,7 +309,7 @@ struct sh_pfc_soc_info {
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const u16 *pinmux_data;
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unsigned int pinmux_data_size;
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u32 unlock_reg;
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u32 unlock_reg; /* can be literal address or mask */
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};
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extern const struct sh_pfc_soc_info emev2_pinmux_info;
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@ -331,6 +340,7 @@ extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
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extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
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extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
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extern const struct sh_pfc_soc_info sh7203_pinmux_info;
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extern const struct sh_pfc_soc_info sh7264_pinmux_info;
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extern const struct sh_pfc_soc_info sh7269_pinmux_info;
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@ -451,9 +461,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
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fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
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#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
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#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
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#define PORT_GP_CFG_2(bank, fn, sfx, cfg) \
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PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
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#define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0)
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#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
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PORT_GP_CFG_2(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
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#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
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@ -572,9 +586,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
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PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
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#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
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#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
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#define PORT_GP_CFG_31(bank, fn, sfx, cfg) \
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PORT_GP_CFG_30(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
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#define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0)
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#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
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PORT_GP_CFG_31(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
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#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
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