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Blackfin arch: all our other ports call this SIZE rather than SPI_LEN
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
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2 changed files with 2 additions and 2 deletions
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@ -928,7 +928,7 @@
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#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
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#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
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#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
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#define SPI_LEN 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
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#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
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#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
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#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
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#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
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@ -1165,7 +1165,7 @@
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#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
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#define PSSE 0x0010 /* Slave-Select Input Enable */
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#define EMISO 0x0020 /* Enable MISO As Output */
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#define SPI_SIZE 0x0100 /* Size of Words (16/8* Bits) */
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#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
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#define LSBF 0x0200 /* LSB First */
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#define CPHA 0x0400 /* Clock Phase */
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#define CPOL 0x0800 /* Clock Polarity */
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