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crypto: hisilicon - add device error report through abnormal irq
By configuring the device error in firmware to report through abnormal interruption, process all NFE errors in irq handler. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Shukun Tan
Herbert Xu
parent
3176637ac1
commit
dbdc1ec31f
2 changed files with 187 additions and 153 deletions
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@ -219,6 +219,12 @@ enum vft_type {
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CQC_VFT,
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};
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enum acc_err_result {
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ACC_ERR_NONE,
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ACC_ERR_NEED_RESET,
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ACC_ERR_RECOVERED,
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};
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struct qm_cqe {
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__le32 rsvd0;
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__le16 cmd_id;
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@ -315,7 +321,7 @@ struct hisi_qm_hw_ops {
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int (*debug_init)(struct hisi_qm *qm);
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void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe);
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void (*hw_error_uninit)(struct hisi_qm *qm);
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pci_ers_result_t (*hw_error_handle)(struct hisi_qm *qm);
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enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
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};
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static const char * const qm_debug_file_name[] = {
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@ -704,46 +710,6 @@ static irqreturn_t qm_aeq_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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static irqreturn_t qm_abnormal_irq(int irq, void *data)
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{
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return IRQ_HANDLED;
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}
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static int qm_irq_register(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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int ret;
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ret = request_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR),
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qm_irq, IRQF_SHARED, qm->dev_name, qm);
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if (ret)
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return ret;
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if (qm->ver == QM_HW_V2) {
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ret = request_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR),
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qm_aeq_irq, IRQF_SHARED, qm->dev_name, qm);
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if (ret)
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goto err_aeq_irq;
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if (qm->fun_type == QM_HW_PF) {
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ret = request_irq(pci_irq_vector(pdev,
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QM_ABNORMAL_EVENT_IRQ_VECTOR),
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qm_abnormal_irq, IRQF_SHARED,
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qm->dev_name, qm);
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if (ret)
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goto err_abonormal_irq;
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}
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}
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return 0;
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err_abonormal_irq:
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free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
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err_aeq_irq:
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free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
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return ret;
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}
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static void qm_irq_unregister(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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@ -1163,7 +1129,7 @@ static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
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}
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}
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static pci_ers_result_t qm_hw_error_handle_v2(struct hisi_qm *qm)
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static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)
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{
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u32 error_status, tmp;
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@ -1179,13 +1145,13 @@ static pci_ers_result_t qm_hw_error_handle_v2(struct hisi_qm *qm)
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if (error_status == QM_DB_RANDOM_INVALID) {
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writel(error_status, qm->io_base +
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QM_ABNORMAL_INT_SOURCE);
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return PCI_ERS_RESULT_RECOVERED;
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return ACC_ERR_RECOVERED;
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}
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return PCI_ERS_RESULT_NEED_RESET;
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return ACC_ERR_NEED_RESET;
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}
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return PCI_ERS_RESULT_RECOVERED;
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return ACC_ERR_RECOVERED;
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}
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static const struct hisi_qm_hw_ops qm_hw_ops_v1 = {
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@ -1942,100 +1908,6 @@ static void hisi_qm_pre_init(struct hisi_qm *qm)
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qm->qp_in_used = 0;
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}
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/**
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* hisi_qm_init() - Initialize configures about qm.
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* @qm: The qm needing init.
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*
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* This function init qm, then we can call hisi_qm_start to put qm into work.
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*/
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int hisi_qm_init(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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struct device *dev = &pdev->dev;
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unsigned int num_vec;
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int ret;
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hisi_qm_pre_init(qm);
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ret = qm_alloc_uacce(qm);
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if (ret < 0)
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dev_warn(&pdev->dev, "fail to alloc uacce (%d)\n", ret);
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ret = pci_enable_device_mem(pdev);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to enable device mem!\n");
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goto err_remove_uacce;
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}
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ret = pci_request_mem_regions(pdev, qm->dev_name);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to request mem regions!\n");
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goto err_disable_pcidev;
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}
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qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
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qm->phys_size = pci_resource_len(qm->pdev, PCI_BAR_2);
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qm->io_base = ioremap(qm->phys_base, qm->phys_size);
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if (!qm->io_base) {
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ret = -EIO;
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goto err_release_mem_regions;
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}
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
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if (ret < 0)
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goto err_iounmap;
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pci_set_master(pdev);
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if (!qm->ops->get_irq_num) {
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ret = -EOPNOTSUPP;
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goto err_iounmap;
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}
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num_vec = qm->ops->get_irq_num(qm);
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ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI);
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if (ret < 0) {
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dev_err(dev, "Failed to enable MSI vectors!\n");
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goto err_iounmap;
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}
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ret = qm_irq_register(qm);
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if (ret)
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goto err_free_irq_vectors;
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if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V2) {
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/* v2 starts to support get vft by mailbox */
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ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
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if (ret)
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goto err_irq_unregister;
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}
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ret = hisi_qm_memory_init(qm);
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if (ret)
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goto err_irq_unregister;
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INIT_WORK(&qm->work, qm_work_process);
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atomic_set(&qm->status.flags, QM_INIT);
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return 0;
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err_irq_unregister:
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qm_irq_unregister(qm);
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err_free_irq_vectors:
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pci_free_irq_vectors(pdev);
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err_iounmap:
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iounmap(qm->io_base);
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err_release_mem_regions:
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pci_release_mem_regions(pdev);
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err_disable_pcidev:
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pci_disable_device(pdev);
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err_remove_uacce:
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uacce_remove(qm->uacce);
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qm->uacce = NULL;
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return ret;
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}
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EXPORT_SYMBOL_GPL(hisi_qm_init);
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/**
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* hisi_qm_uninit() - Uninitialize qm.
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* @qm: The qm needed uninit.
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@ -2460,11 +2332,11 @@ static void qm_hw_error_uninit(struct hisi_qm *qm)
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qm->ops->hw_error_uninit(qm);
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}
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static pci_ers_result_t qm_hw_error_handle(struct hisi_qm *qm)
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static enum acc_err_result qm_hw_error_handle(struct hisi_qm *qm)
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{
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if (!qm->ops->hw_error_handle) {
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dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
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return PCI_ERS_RESULT_NONE;
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return ACC_ERR_NONE;
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}
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return qm->ops->hw_error_handle(qm);
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@ -2777,13 +2649,13 @@ int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs)
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}
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EXPORT_SYMBOL_GPL(hisi_qm_sriov_configure);
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static pci_ers_result_t qm_dev_err_handle(struct hisi_qm *qm)
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static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)
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{
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u32 err_sts;
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if (!qm->err_ini->get_dev_hw_err_status) {
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dev_err(&qm->pdev->dev, "Device doesn't support get hw error status!\n");
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return PCI_ERS_RESULT_NONE;
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return ACC_ERR_NONE;
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}
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/* get device hardware error status */
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@ -2794,20 +2666,19 @@ static pci_ers_result_t qm_dev_err_handle(struct hisi_qm *qm)
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if (!qm->err_ini->log_dev_hw_err) {
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dev_err(&qm->pdev->dev, "Device doesn't support log hw error!\n");
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return PCI_ERS_RESULT_NEED_RESET;
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return ACC_ERR_NEED_RESET;
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}
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qm->err_ini->log_dev_hw_err(qm, err_sts);
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return PCI_ERS_RESULT_NEED_RESET;
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return ACC_ERR_NEED_RESET;
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}
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return PCI_ERS_RESULT_RECOVERED;
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return ACC_ERR_RECOVERED;
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}
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static pci_ers_result_t qm_process_dev_error(struct pci_dev *pdev)
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static enum acc_err_result qm_process_dev_error(struct hisi_qm *qm)
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{
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struct hisi_qm *qm = pci_get_drvdata(pdev);
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pci_ers_result_t qm_ret, dev_ret;
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enum acc_err_result qm_ret, dev_ret;
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/* log qm error */
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qm_ret = qm_hw_error_handle(qm);
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@ -2815,9 +2686,9 @@ static pci_ers_result_t qm_process_dev_error(struct pci_dev *pdev)
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/* log device error */
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dev_ret = qm_dev_err_handle(qm);
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return (qm_ret == PCI_ERS_RESULT_NEED_RESET ||
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dev_ret == PCI_ERS_RESULT_NEED_RESET) ?
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PCI_ERS_RESULT_NEED_RESET : PCI_ERS_RESULT_RECOVERED;
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return (qm_ret == ACC_ERR_NEED_RESET ||
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dev_ret == ACC_ERR_NEED_RESET) ?
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ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED;
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}
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/**
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@ -2831,6 +2702,9 @@ static pci_ers_result_t qm_process_dev_error(struct pci_dev *pdev)
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pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
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pci_channel_state_t state)
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{
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struct hisi_qm *qm = pci_get_drvdata(pdev);
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enum acc_err_result ret;
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if (pdev->is_virtfn)
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return PCI_ERS_RESULT_NONE;
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@ -2838,7 +2712,11 @@ pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
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if (state == pci_channel_io_perm_failure)
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return PCI_ERS_RESULT_DISCONNECT;
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return qm_process_dev_error(pdev);
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ret = qm_process_dev_error(qm);
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if (ret == ACC_ERR_NEED_RESET)
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return PCI_ERS_RESULT_NEED_RESET;
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return PCI_ERS_RESULT_RECOVERED;
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}
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EXPORT_SYMBOL_GPL(hisi_qm_dev_err_detected);
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@ -3428,6 +3306,161 @@ void hisi_qm_reset_done(struct pci_dev *pdev)
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}
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EXPORT_SYMBOL_GPL(hisi_qm_reset_done);
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static irqreturn_t qm_abnormal_irq(int irq, void *data)
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{
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struct hisi_qm *qm = data;
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enum acc_err_result ret;
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ret = qm_process_dev_error(qm);
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if (ret == ACC_ERR_NEED_RESET)
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schedule_work(&qm->rst_work);
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return IRQ_HANDLED;
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}
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static int qm_irq_register(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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int ret;
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ret = request_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR),
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qm_irq, IRQF_SHARED, qm->dev_name, qm);
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if (ret)
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return ret;
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if (qm->ver == QM_HW_V2) {
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ret = request_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR),
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qm_aeq_irq, IRQF_SHARED, qm->dev_name, qm);
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if (ret)
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goto err_aeq_irq;
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if (qm->fun_type == QM_HW_PF) {
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ret = request_irq(pci_irq_vector(pdev,
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QM_ABNORMAL_EVENT_IRQ_VECTOR),
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qm_abnormal_irq, IRQF_SHARED,
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qm->dev_name, qm);
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if (ret)
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goto err_abonormal_irq;
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}
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}
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return 0;
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err_abonormal_irq:
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free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
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err_aeq_irq:
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free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
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return ret;
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}
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static void hisi_qm_controller_reset(struct work_struct *rst_work)
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{
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struct hisi_qm *qm = container_of(rst_work, struct hisi_qm, rst_work);
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int ret;
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/* reset pcie device controller */
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ret = qm_controller_reset(qm);
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if (ret)
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dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret);
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}
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/**
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* hisi_qm_init() - Initialize configures about qm.
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* @qm: The qm needing init.
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*
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* This function init qm, then we can call hisi_qm_start to put qm into work.
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*/
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int hisi_qm_init(struct hisi_qm *qm)
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{
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struct pci_dev *pdev = qm->pdev;
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struct device *dev = &pdev->dev;
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unsigned int num_vec;
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int ret;
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hisi_qm_pre_init(qm);
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ret = qm_alloc_uacce(qm);
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if (ret < 0)
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dev_warn(&pdev->dev, "fail to alloc uacce (%d)\n", ret);
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ret = pci_enable_device_mem(pdev);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to enable device mem!\n");
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goto err_remove_uacce;
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}
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ret = pci_request_mem_regions(pdev, qm->dev_name);
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if (ret < 0) {
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dev_err(&pdev->dev, "Failed to request mem regions!\n");
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goto err_disable_pcidev;
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}
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qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
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qm->phys_size = pci_resource_len(qm->pdev, PCI_BAR_2);
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qm->io_base = ioremap(qm->phys_base, qm->phys_size);
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if (!qm->io_base) {
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ret = -EIO;
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goto err_release_mem_regions;
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}
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
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if (ret < 0)
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goto err_iounmap;
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pci_set_master(pdev);
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if (!qm->ops->get_irq_num) {
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ret = -EOPNOTSUPP;
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goto err_iounmap;
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}
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num_vec = qm->ops->get_irq_num(qm);
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ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI);
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if (ret < 0) {
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dev_err(dev, "Failed to enable MSI vectors!\n");
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goto err_iounmap;
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}
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ret = qm_irq_register(qm);
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if (ret)
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goto err_free_irq_vectors;
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if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V2) {
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/* v2 starts to support get vft by mailbox */
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ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
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if (ret)
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goto err_irq_unregister;
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}
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ret = hisi_qm_memory_init(qm);
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if (ret)
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goto err_irq_unregister;
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INIT_WORK(&qm->work, qm_work_process);
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if (qm->fun_type == QM_HW_PF)
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INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);
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||||
|
||||
atomic_set(&qm->status.flags, QM_INIT);
|
||||
|
||||
return 0;
|
||||
|
||||
err_irq_unregister:
|
||||
qm_irq_unregister(qm);
|
||||
err_free_irq_vectors:
|
||||
pci_free_irq_vectors(pdev);
|
||||
err_iounmap:
|
||||
iounmap(qm->io_base);
|
||||
err_release_mem_regions:
|
||||
pci_release_mem_regions(pdev);
|
||||
err_disable_pcidev:
|
||||
pci_disable_device(pdev);
|
||||
err_remove_uacce:
|
||||
uacce_remove(qm->uacce);
|
||||
qm->uacce = NULL;
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hisi_qm_init);
|
||||
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
|
||||
MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver");
|
||||
|
|
|
|||
|
|
@ -226,6 +226,7 @@ struct hisi_qm {
|
|||
|
||||
struct workqueue_struct *wq;
|
||||
struct work_struct work;
|
||||
struct work_struct rst_work;
|
||||
|
||||
const char *algs;
|
||||
bool use_sva;
|
||||
|
|
|
|||
Loading…
Reference in a new issue