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drm/i915/tgl: Don't treat unslice registers as masked
The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2 registers that we update in a few engine workarounds are not masked registers (i.e., we don't have to write a mask bit in the top 16 bits when updating one of the lower 16 bits). As such, these workarounds should be applied via wa_write_or() rather than wa_masked_en() v2: - Rebase Reported-by: Nick Desaulniers <ndesaulniers@google.com> Reported-by: kernelci.org bot <bot@kernelci.org> References: https://github.com/ClangBuiltLinux/linux/issues/918 Fixes:50148a25f8
("drm/i915/tgl: Move and restrict Wa_1408615072") Fixes:3551ff9287
("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()") Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200306171139.1414649-1-matthew.d.roper@intel.com
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1 changed files with 6 additions and 6 deletions
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@ -1382,7 +1382,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
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/* Wa_1408615072:tgl */
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wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
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wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
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VSUNIT_CLKGATE_DIS_TGL);
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}
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@ -1472,11 +1472,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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* Wa_1408615072:icl,ehl (vsunit)
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* Wa_1407596294:icl,ehl (hsunit)
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*/
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wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
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wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
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VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
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/* Wa_1407352427:icl,ehl */
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wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
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wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
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PSDUNIT_CLKGATE_DIS);
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}
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