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ARM: shmobile: r8a7740: add DMAEngine support for USB
Current shdmac can support USB DMAC on r8a7740. This support reduce CPU duty when USB access. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This commit is contained in:
Kuninori Morimoto
Rafael J. Wysocki
parent
cb76eb812e
commit
dbf382e556
3 changed files with 92 additions and 1 deletions
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@ -463,7 +463,7 @@ enum {
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MSTP230,
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MSTP222,
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MSTP218, MSTP217, MSTP216,
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MSTP218, MSTP217, MSTP216, MSTP214,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP329, MSTP328, MSTP323, MSTP320,
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@ -489,6 +489,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
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[MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
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[MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
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[MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
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[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
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[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
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[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
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@ -567,6 +568,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
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CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
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CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
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CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
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CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
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@ -600,6 +600,8 @@ enum {
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SHDMA_SLAVE_FSIA_RX,
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SHDMA_SLAVE_FSIA_TX,
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SHDMA_SLAVE_FSIB_TX,
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SHDMA_SLAVE_USBHS_TX,
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SHDMA_SLAVE_USBHS_RX,
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};
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#endif /* __ASM_R8A7740_H__ */
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@ -501,6 +501,92 @@ static struct platform_device dma2_device = {
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},
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};
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/* USB-DMAC */
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/* Transmit sizes and respective CHCR register values */
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enum {
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USBTS_XMIT_SZ_8BYTE = 0,
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USBTS_XMIT_SZ_16BYTE = 1,
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USBTS_XMIT_SZ_32BYTE = 2,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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static const unsigned int dma_usbts_shift[] = {
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[USBTS_XMIT_SZ_8BYTE] = 3,
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[USBTS_XMIT_SZ_16BYTE] = 4,
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[USBTS_XMIT_SZ_32BYTE] = 5,
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};
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static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
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{
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.offset = 0,
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}, {
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.offset = 0x20,
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},
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};
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#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
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static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_USBHS_TX,
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.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
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}, {
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.slave_id = SHDMA_SLAVE_USBHS_RX,
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.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
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},
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};
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static struct sh_dmae_pdata usb_dma_platform_data = {
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.slave = r8a7740_usb_dma_slaves,
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.slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
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.channel = r8a7740_usb_dma_channels,
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.channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
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.ts_low_shift = 6,
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.ts_low_mask = 0xc0,
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.ts_high_shift = 0,
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.ts_high_mask = 0,
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.ts_shift = dma_usbts_shift,
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.ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
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.dmaor_init = DMAOR_DME,
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.chcr_offset = 0x14,
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.chcr_ie_bit = 1 << 5,
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.dmaor_is_32bit = 1,
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.needs_tend_set = 1,
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.no_dmars = 1,
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.slave_only = 1,
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};
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static struct resource r8a7740_usb_dma_resources[] = {
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{
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/* Channel registers and DMAOR */
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.start = 0xe68a0020,
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.end = 0xe68a0064 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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/* VCR/SWR/DMICR */
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.start = 0xe68a0000,
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.end = 0xe68a0014 - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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/* IRQ for channels */
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.start = evt2irq(0x0a00),
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.end = evt2irq(0x0a00),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device usb_dma_device = {
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.name = "sh-dma-engine",
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.id = 3,
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.resource = r8a7740_usb_dma_resources,
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.num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
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.dev = {
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.platform_data = &usb_dma_platform_data,
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},
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};
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/* I2C */
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static struct resource i2c0_resources[] = {
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[0] = {
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@ -550,6 +636,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
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&dma0_device,
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&dma1_device,
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&dma2_device,
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&usb_dma_device,
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};
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/*
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