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drm/amdgpu: Fix the exported always on CU bitmap
Newer asics with 4 SEs are not able to fit the entire bitmask in the original field, use an array instead. v2: keep cu_ao_mask for backward compatibility. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8 changed files with 24 additions and 7 deletions
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@ -1028,12 +1028,15 @@ struct amdgpu_gfx_config {
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};
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struct amdgpu_cu_info {
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uint32_t number; /* total active CU number */
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uint32_t ao_cu_mask;
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uint32_t max_waves_per_simd;
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uint32_t wave_front_size;
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uint32_t max_scratch_slots_per_cu;
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uint32_t lds_size;
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/* total active CU number */
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uint32_t number;
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uint32_t ao_cu_mask;
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uint32_t ao_cu_bitmap[4][4];
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uint32_t bitmap[4][4];
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};
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@ -67,9 +67,10 @@
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* - 3.15.0 - Export more gpu info for gfx9
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* - 3.16.0 - Add reserved vmid support
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* - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
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* - 3.18.0 - Export gpu always on cu bitmap
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*/
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#define KMS_DRIVER_MAJOR 3
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#define KMS_DRIVER_MINOR 17
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#define KMS_DRIVER_MINOR 18
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#define KMS_DRIVER_PATCHLEVEL 0
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int amdgpu_vram_limit = 0;
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@ -594,6 +594,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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dev_info.cu_active_number = adev->gfx.cu_info.number;
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dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
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dev_info.ce_ram_size = adev->gfx.ce_ram_size;
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memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
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sizeof(adev->gfx.cu_info.ao_cu_bitmap));
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memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
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sizeof(adev->gfx.cu_info.bitmap));
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dev_info.vram_type = adev->mc.vram_type;
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@ -3535,7 +3535,9 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
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mask <<= 1;
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}
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active_cu_number += counter;
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ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
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if (i < 2 && j < 2)
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ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
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cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
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}
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}
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@ -5427,7 +5427,9 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
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mask <<= 1;
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}
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active_cu_number += counter;
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ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
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if (i < 2 && j < 2)
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ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
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cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
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}
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}
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gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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@ -7087,7 +7087,9 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
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mask <<= 1;
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}
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active_cu_number += counter;
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ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
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if (i < 2 && j < 2)
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ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
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cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
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}
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}
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gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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@ -4459,7 +4459,9 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
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mask <<= 1;
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}
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active_cu_number += counter;
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ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
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if (i < 2 && j < 2)
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ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
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cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
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}
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}
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gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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@ -764,6 +764,7 @@ struct drm_amdgpu_info_device {
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__u64 max_memory_clock;
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/* cu information */
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__u32 cu_active_number;
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/* NOTE: cu_ao_mask is INVALID, DON'T use it */
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__u32 cu_ao_mask;
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__u32 cu_bitmap[4][4];
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/** Render backend pipe mask. One render backend is CB+DB. */
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@ -818,6 +819,8 @@ struct drm_amdgpu_info_device {
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/* max gs wavefront per vgt*/
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__u32 max_gs_waves_per_vgt;
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__u32 _pad1;
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/* always on cu bitmap */
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__u32 cu_ao_bitmap[4][4];
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};
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struct drm_amdgpu_info_hw_ip {
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