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riscv: Fixup obvious bug for fp-regs reset
CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_misa register.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
[paul.walmsley@sifive.com: fix typo in commit message]
Fixes: 9e80635619
("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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1 changed files with 1 additions and 1 deletions
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@ -251,7 +251,7 @@ ENTRY(reset_regs)
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#ifdef CONFIG_FPU
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#ifdef CONFIG_FPU
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csrr t0, CSR_MISA
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csrr t0, CSR_MISA
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andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
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andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
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bnez t0, .Lreset_regs_done
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beqz t0, .Lreset_regs_done
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li t1, SR_FS
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li t1, SR_FS
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csrs CSR_STATUS, t1
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csrs CSR_STATUS, t1
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