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Code Issues Releases Wiki Activity

drm/nouveau: store supported dma mask in vmmgr

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-09-26 14:37:51 +10:00
parent c0abf5c9fa
commit dc73b45ad4
7 changed files with 9 additions and 7 deletions
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1
drivers/gpu/drm/nouveau/core/include/subdev/vm.h
View file

@ -69,6 +69,7 @@ struct nouveau_vmmgr {
struct nouveau_subdev base;
u64 limit;
u8 dma_bits;
u32 pgt_bits;
u8 spg_shift;
u8 lpg_shift;

1
drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c
View file

@ -97,6 +97,7 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.create = nv04_vm_create;
priv->base.limit = NV04_PDMA_SIZE;
priv->base.dma_bits = 32;
priv->base.pgt_bits = 32 - 12;
priv->base.spg_shift = 12;
priv->base.lpg_shift = 12;

1
drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
View file

@ -98,6 +98,7 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.create = nv04_vm_create;
priv->base.limit = NV41_GART_SIZE;
priv->base.dma_bits = 39;
priv->base.pgt_bits = 32 - 12;
priv->base.spg_shift = 12;
priv->base.lpg_shift = 12;

1
drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c
View file

@ -179,6 +179,7 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->base.create = nv04_vm_create;
priv->base.limit = NV44_GART_SIZE;
priv->base.dma_bits = 39;
priv->base.pgt_bits = 32 - 12;
priv->base.spg_shift = 12;
priv->base.lpg_shift = 12;

1
drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
View file

@ -201,6 +201,7 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
priv->base.limit = 1ULL << 40;
priv->base.dma_bits = 40;
priv->base.pgt_bits = 29 - 12;
priv->base.spg_shift = 12;
priv->base.lpg_shift = 16;

1
drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
View file

@ -163,6 +163,7 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return ret;
priv->base.limit = 1ULL << 40;
priv->base.dma_bits = 40;
priv->base.pgt_bits = 27 - 12;
priv->base.spg_shift = 12;
priv->base.lpg_shift = 17;

10
drivers/gpu/drm/nouveau/nouveau_ttm.c
View file

@ -340,14 +340,10 @@ nouveau_ttm_init(struct nouveau_drm *drm)
u32 bits;
int ret;
if (nv_device(drm->device)->card_type >= NV_50) {
if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
bits = 40;
else
bits = 32;
} else {
bits = nouveau_vmmgr(drm->device)->dma_bits;
if ( drm->agp.stat == ENABLED ||
!pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits)))
bits = 32;
}
ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits));
if (ret)