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clk: JZ4780: Add functions for enable and disable USB PHY.
Add new functions to "jz4780_otg_phy_ops" to enable or disable the USB PHY in the JZ4780 SoC. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20200630163852.47267-2-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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82df5b7329
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1 changed files with 35 additions and 30 deletions
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@ -4,6 +4,7 @@
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*
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* Copyright (c) 2013-2015 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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* Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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*/
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#include <linux/clk-provider.h>
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@ -59,6 +60,7 @@
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#define USBPCR_VBUSVLDEXT BIT(24)
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#define USBPCR_VBUSVLDEXTSEL BIT(23)
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#define USBPCR_POR BIT(22)
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#define USBPCR_SIDDQ BIT(21)
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#define USBPCR_OTG_DISABLE BIT(20)
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#define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
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#define USBPCR_OTGTUNE_MASK (0x7 << 14)
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@ -100,32 +102,6 @@
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static struct ingenic_cgu *cgu;
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static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)
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{
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/* we only use CLKCORE, revisit if that ever changes */
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return 0;
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}
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static int jz4780_otg_phy_set_parent(struct clk_hw *hw, u8 idx)
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{
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unsigned long flags;
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u32 usbpcr1;
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if (idx > 0)
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return -EINVAL;
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spin_lock_irqsave(&cgu->lock, flags);
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usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
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usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK;
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/* we only use CLKCORE */
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usbpcr1 |= USBPCR1_REFCLKSEL_CORE;
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writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return 0;
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}
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static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -149,7 +125,6 @@ static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
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return 19200000;
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}
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BUG();
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return parent_rate;
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}
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@ -206,13 +181,43 @@ static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
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return 0;
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}
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static const struct clk_ops jz4780_otg_phy_ops = {
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.get_parent = jz4780_otg_phy_get_parent,
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.set_parent = jz4780_otg_phy_set_parent,
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static int jz4780_otg_phy_enable(struct clk_hw *hw)
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{
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
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writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
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writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
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return 0;
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}
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static void jz4780_otg_phy_disable(struct clk_hw *hw)
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{
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
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writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
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writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
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}
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static int jz4780_otg_phy_is_enabled(struct clk_hw *hw)
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{
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
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return (readl(reg_opcr) & OPCR_SPENDN0) &&
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!(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
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!(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
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}
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static const struct clk_ops jz4780_otg_phy_ops = {
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.recalc_rate = jz4780_otg_phy_recalc_rate,
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.round_rate = jz4780_otg_phy_round_rate,
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.set_rate = jz4780_otg_phy_set_rate,
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.enable = jz4780_otg_phy_enable,
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.disable = jz4780_otg_phy_disable,
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.is_enabled = jz4780_otg_phy_is_enabled,
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};
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static int jz4780_core1_enable(struct clk_hw *hw)
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