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media: dt-bindings: media: mtk-vcodec: Separating mtk vcodec encoder node
Updates binding document since the avc and vp8 hardware encoder in MT8173 are now separated. Separate "mediatek,mt8173-vcodec-enc" to "mediatek,mt8173-vcodec-enc-vp8" and "mediatek,mt8173-vcodec-enc". This patch is not a compatible change, but we must do this modifaction because MediaTek IOMMU add the device_link between the smi-larb device and venc_device, if the venc device call the pm_runtime_get_sync, the smi-larb's pm_runtime_get_sync also be called automatically. There is a bit of backward compatibility for avc encoder, the avc encoder device node still has compatible "mediatek,mt8173-vcodec-enc". Acked-by: Tiffany Lin <tiffany.lin@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com> Signed-off-by: Irui Wang <irui.wang@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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1 changed files with 29 additions and 26 deletions
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@ -4,7 +4,9 @@ Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
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supports high resolution encoding and decoding functionalities.
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Required properties:
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- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder
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- compatible : must be one of the following string:
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"mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
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"mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
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"mediatek,mt8183-vcodec-enc" for MT8183 encoder.
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"mediatek,mt8173-vcodec-dec" for MT8173 decoder.
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- reg : Physical base address of the video codec registers and length of
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@ -13,10 +15,10 @@ Required properties:
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- mediatek,larb : must contain the local arbiters in the current Socs.
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- clocks : list of clock specifiers, corresponding to entries in
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the clock-names property.
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- clock-names: encoder must contain "venc_sel_src", "venc_sel",,
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"venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",
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"univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
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"venc_lt_sel", "vdec_bus_clk_src".
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- clock-names: avc encoder must contain "venc_sel", vp8 encoder must
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contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2",
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"clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel",
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"vdec_bus_clk_src".
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- iommus : should point to the respective IOMMU block with master port as
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argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
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for details.
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@ -80,14 +82,10 @@ vcodec_dec: vcodec@16000000 {
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assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
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};
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vcodec_enc: vcodec@18002000 {
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vcodec_enc_avc: vcodec@18002000 {
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compatible = "mediatek,mt8173-vcodec-enc";
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reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
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<0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
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mediatek,larb = <&larb3>,
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<&larb5>;
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reg = <0 0x18002000 0 0x1000>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_VENC_RCPU>,
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<&iommu M4U_PORT_VENC_REC>,
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<&iommu M4U_PORT_VENC_BSDMA>,
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@ -98,8 +96,20 @@ vcodec_dec: vcodec@16000000 {
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<&iommu M4U_PORT_VENC_REF_LUMA>,
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<&iommu M4U_PORT_VENC_REF_CHROMA>,
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<&iommu M4U_PORT_VENC_NBM_RDMA>,
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<&iommu M4U_PORT_VENC_NBM_WDMA>,
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<&iommu M4U_PORT_VENC_RCPU_SET2>,
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<&iommu M4U_PORT_VENC_NBM_WDMA>;
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mediatek,larb = <&larb3>;
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mediatek,vpu = <&vpu>;
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clocks = <&topckgen CLK_TOP_VENC_SEL>;
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clock-names = "venc_sel";
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assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
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};
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vcodec_enc_vp8: vcodec@19002000 {
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compatible = "mediatek,mt8173-vcodec-enc-vp8";
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reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
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<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
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<&iommu M4U_PORT_VENC_BSDMA_SET2>,
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<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
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@ -108,17 +118,10 @@ vcodec_dec: vcodec@16000000 {
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<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
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<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
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<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
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mediatek,larb = <&larb5>;
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mediatek,vpu = <&vpu>;
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clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
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<&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_UNIVPLL1_D2>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "venc_sel_src",
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"venc_sel",
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"venc_lt_sel_src",
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"venc_lt_sel";
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assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
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<&topckgen CLK_TOP_UNIVPLL1_D2>;
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clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "venc_lt_sel";
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assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
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};
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