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drm/exynos: gsc: Fix support for NV16/61, YUV420/YVU420 and YUV422 modes
Fix following issues related to planar YUV pixel format configuration: - NV16/61 modes were incorrectly programmed as NV12/21, - YVU420 was programmed as YUV420 on source, - YVU420 and YUV422 were programmed as YUV420 on output. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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parent
4cc11a5f53
commit
dd209ef809
2 changed files with 21 additions and 9 deletions
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@ -492,21 +492,25 @@ static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt)
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GSC_IN_CHROMA_ORDER_CRCB);
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GSC_IN_CHROMA_ORDER_CRCB);
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break;
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break;
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case DRM_FORMAT_NV21:
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case DRM_FORMAT_NV21:
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cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
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break;
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case DRM_FORMAT_NV61:
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case DRM_FORMAT_NV61:
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cfg |= (GSC_IN_CHROMA_ORDER_CRCB |
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cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
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GSC_IN_YUV420_2P);
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break;
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break;
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case DRM_FORMAT_YUV422:
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case DRM_FORMAT_YUV422:
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cfg |= GSC_IN_YUV422_3P;
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cfg |= GSC_IN_YUV422_3P;
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break;
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break;
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case DRM_FORMAT_YUV420:
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case DRM_FORMAT_YUV420:
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cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
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break;
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case DRM_FORMAT_YVU420:
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case DRM_FORMAT_YVU420:
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cfg |= GSC_IN_YUV420_3P;
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cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
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break;
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break;
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_NV12:
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cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
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break;
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case DRM_FORMAT_NV16:
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case DRM_FORMAT_NV16:
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cfg |= (GSC_IN_CHROMA_ORDER_CBCR |
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cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
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GSC_IN_YUV420_2P);
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break;
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break;
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}
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}
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@ -672,18 +676,25 @@ static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt)
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GSC_OUT_CHROMA_ORDER_CRCB);
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GSC_OUT_CHROMA_ORDER_CRCB);
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break;
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break;
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case DRM_FORMAT_NV21:
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case DRM_FORMAT_NV21:
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case DRM_FORMAT_NV61:
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cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
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cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
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break;
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break;
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case DRM_FORMAT_NV61:
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cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
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break;
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case DRM_FORMAT_YUV422:
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case DRM_FORMAT_YUV422:
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cfg |= GSC_OUT_YUV422_3P;
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break;
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case DRM_FORMAT_YUV420:
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case DRM_FORMAT_YUV420:
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cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
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break;
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case DRM_FORMAT_YVU420:
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case DRM_FORMAT_YVU420:
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cfg |= GSC_OUT_YUV420_3P;
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cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
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break;
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break;
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_NV12:
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cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
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break;
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case DRM_FORMAT_NV16:
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case DRM_FORMAT_NV16:
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cfg |= (GSC_OUT_CHROMA_ORDER_CBCR |
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cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
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GSC_OUT_YUV420_2P);
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break;
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break;
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}
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}
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@ -138,6 +138,7 @@
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#define GSC_OUT_YUV420_3P (3 << 4)
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#define GSC_OUT_YUV420_3P (3 << 4)
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#define GSC_OUT_YUV422_1P (4 << 4)
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#define GSC_OUT_YUV422_1P (4 << 4)
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#define GSC_OUT_YUV422_2P (5 << 4)
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#define GSC_OUT_YUV422_2P (5 << 4)
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#define GSC_OUT_YUV422_3P (6 << 4)
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#define GSC_OUT_YUV444 (7 << 4)
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#define GSC_OUT_YUV444 (7 << 4)
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#define GSC_OUT_TILE_TYPE_MASK (1 << 2)
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#define GSC_OUT_TILE_TYPE_MASK (1 << 2)
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#define GSC_OUT_TILE_C_16x8 (0 << 2)
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#define GSC_OUT_TILE_C_16x8 (0 << 2)
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