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drm/i915: Fix PCH reference clock for FDI on HSW/BDW
The change to skip the PCH reference initialization during fastboot
did end up breaking FDI. To fix that let's try to do the PCH reference
init whenever we're disabling a DPLL that was using said reference
previously.
Cc: stable@vger.kernel.org
Tested-by: Andrija <akijo97@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112084
Fixes: b16c7ed95c
("drm/i915: Do not touch the PCH SSC reference if a PLL is using it")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191022185643.1483-1-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
This commit is contained in:
parent
2728200f48
commit
dd5279c714
3 changed files with 23 additions and 5 deletions
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@ -9432,7 +9432,6 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
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static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
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{
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struct intel_encoder *encoder;
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bool pch_ssc_in_use = false;
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bool has_fdi = false;
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for_each_intel_encoder(&dev_priv->drm, encoder) {
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@ -9460,22 +9459,24 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
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* clock hierarchy. That would also allow us to do
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* clock bending finally.
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*/
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dev_priv->pch_ssc_use = 0;
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if (spll_uses_pch_ssc(dev_priv)) {
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DRM_DEBUG_KMS("SPLL using PCH SSC\n");
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pch_ssc_in_use = true;
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dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL);
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}
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if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
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DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n");
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pch_ssc_in_use = true;
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dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
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}
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if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
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DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n");
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pch_ssc_in_use = true;
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dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
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}
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if (pch_ssc_in_use)
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if (dev_priv->pch_ssc_use)
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return;
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if (has_fdi) {
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@ -526,16 +526,31 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
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val = I915_READ(WRPLL_CTL(id));
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I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
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POSTING_READ(WRPLL_CTL(id));
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/*
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* Try to set up the PCH reference clock once all DPLLs
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* that depend on it have been shut down.
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*/
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if (dev_priv->pch_ssc_use & BIT(id))
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intel_init_pch_refclk(dev_priv);
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}
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static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll)
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{
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enum intel_dpll_id id = pll->info->id;
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u32 val;
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val = I915_READ(SPLL_CTL);
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I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
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POSTING_READ(SPLL_CTL);
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/*
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* Try to set up the PCH reference clock once all DPLLs
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* that depend on it have been shut down.
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*/
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if (dev_priv->pch_ssc_use & BIT(id))
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intel_init_pch_refclk(dev_priv);
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}
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static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
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@ -1353,6 +1353,8 @@ struct drm_i915_private {
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} contexts;
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} gem;
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u8 pch_ssc_use;
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/* For i915gm/i945gm vblank irq workaround */
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u8 vblank_enabled;
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