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can: sja1000: Add support for the new 4 channel EMS CPC-PCI cards
This patch adds support to the ems_pci driver for the new, v2, 4 channel CPC-PCI/PCIe/104P CAN cards from EMS Dr. Thomas Wuensche. Signed-off-by: Sebastian Haas <haas@ems-wuensche.com> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
69222e2cb0
commit
dd52856ba2
2 changed files with 111 additions and 46 deletions
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@ -61,11 +61,12 @@ config CAN_SJA1000_OF_PLATFORM
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you may want to enable this option.
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config CAN_EMS_PCI
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tristate "EMS CPC-PCI and CPC-PCIe Card"
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tristate "EMS CPC-PCI, CPC-PCIe and CPC-104P Card"
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depends on PCI && CAN_SJA1000
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---help---
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This driver is for the one or two channel CPC-PCI and CPC-PCIe
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cards from EMS Dr. Thomas Wuensche (http://www.ems-wuensche.de).
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This driver is for the one, two or four channel CPC-PCI,
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CPC-PCIe and CPC-104P cards from EMS Dr. Thomas Wuensche
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(http://www.ems-wuensche.de).
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config CAN_KVASER_PCI
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tristate "Kvaser PCIcanx and Kvaser PCIcan PCI Cards"
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@ -32,13 +32,16 @@
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#define DRV_NAME "ems_pci"
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MODULE_AUTHOR("Sebastian Haas <haas@ems-wuenche.com>");
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MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe CAN cards");
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MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe CAN card");
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MODULE_DESCRIPTION("Socket-CAN driver for EMS CPC-PCI/PCIe/104P CAN cards");
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MODULE_SUPPORTED_DEVICE("EMS CPC-PCI/PCIe/104P CAN card");
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MODULE_LICENSE("GPL v2");
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#define EMS_PCI_MAX_CHAN 2
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#define EMS_PCI_V1_MAX_CHAN 2
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#define EMS_PCI_V2_MAX_CHAN 4
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#define EMS_PCI_MAX_CHAN EMS_PCI_V2_MAX_CHAN
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struct ems_pci_card {
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int version;
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int channels;
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struct pci_dev *pci_dev;
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@ -62,13 +65,23 @@ struct ems_pci_card {
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#define PITA2_MISC 0x1c /* Miscellaneous Register */
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#define PITA2_MISC_CONFIG 0x04000000 /* Multiplexed parallel interface */
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/*
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* Register definitions for the PLX 9030
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*/
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#define PLX_ICSR 0x4c /* Interrupt Control/Status register */
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#define PLX_ICSR_LINTI1_ENA 0x0001 /* LINTi1 Enable */
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#define PLX_ICSR_PCIINT_ENA 0x0040 /* PCI Interrupt Enable */
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#define PLX_ICSR_LINTI1_CLR 0x0400 /* Local Edge Triggerable Interrupt Clear */
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#define PLX_ICSR_ENA_CLR (PLX_ICSR_LINTI1_ENA | PLX_ICSR_PCIINT_ENA | \
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PLX_ICSR_LINTI1_CLR)
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/*
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* The board configuration is probably following:
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* RX1 is connected to ground.
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* TX1 is not connected.
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* CLKO is not connected.
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* Setting the OCR register to 0xDA is a good idea.
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* This means normal output mode , push-pull and the correct polarity.
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* This means normal output mode, push-pull and the correct polarity.
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*/
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#define EMS_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
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@ -79,17 +92,21 @@ struct ems_pci_card {
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* is driven by the first one CLKOUT output.
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*/
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#define EMS_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
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#define EMS_PCI_MEM_SIZE 4096 /* Size of the remapped io-memory */
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#define EMS_PCI_V1_BASE_BAR 1
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#define EMS_PCI_V1_MEM_SIZE 4096
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#define EMS_PCI_V2_BASE_BAR 2
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#define EMS_PCI_V2_MEM_SIZE 128
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#define EMS_PCI_CAN_BASE_OFFSET 0x400 /* offset where the controllers starts */
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#define EMS_PCI_CAN_CTRL_SIZE 0x200 /* memory size for each controller */
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#define EMS_PCI_PORT_BYTES 0x4 /* Each register occupies 4 bytes */
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#define EMS_PCI_VENDOR_ID 0x110a /* PCI device and vendor ID */
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#define EMS_PCI_DEVICE_ID 0x2104
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static struct pci_device_id ems_pci_tbl[] = {
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{EMS_PCI_VENDOR_ID, EMS_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
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/* CPC-PCI v1 */
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{PCI_VENDOR_ID_SIEMENS, 0x2104, PCI_ANY_ID, PCI_ANY_ID,},
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/* CPC-PCI v2 */
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{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4000},
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/* CPC-104P v2 */
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{PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_PLX, 0x4002},
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{0,}
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};
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MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
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@ -97,28 +114,47 @@ MODULE_DEVICE_TABLE(pci, ems_pci_tbl);
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/*
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* Helper to read internal registers from card logic (not CAN)
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*/
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static u8 ems_pci_readb(struct ems_pci_card *card, unsigned int port)
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static u8 ems_pci_v1_readb(struct ems_pci_card *card, unsigned int port)
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{
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return readb(card->base_addr + (port * EMS_PCI_PORT_BYTES));
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return readb(card->base_addr + (port * 4));
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}
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static u8 ems_pci_read_reg(const struct sja1000_priv *priv, int port)
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static u8 ems_pci_v1_read_reg(const struct sja1000_priv *priv, int port)
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{
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return readb(priv->reg_base + (port * EMS_PCI_PORT_BYTES));
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return readb(priv->reg_base + (port * 4));
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}
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static void ems_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
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static void ems_pci_v1_write_reg(const struct sja1000_priv *priv,
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int port, u8 val)
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{
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writeb(val, priv->reg_base + (port * EMS_PCI_PORT_BYTES));
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writeb(val, priv->reg_base + (port * 4));
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}
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static void ems_pci_post_irq(const struct sja1000_priv *priv)
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static void ems_pci_v1_post_irq(const struct sja1000_priv *priv)
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{
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struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
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/* reset int flag of pita */
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writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0, card->conf_addr
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+ PITA2_ICR);
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writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
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card->conf_addr + PITA2_ICR);
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}
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static u8 ems_pci_v2_read_reg(const struct sja1000_priv *priv, int port)
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{
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return readb(priv->reg_base + port);
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}
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static void ems_pci_v2_write_reg(const struct sja1000_priv *priv,
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int port, u8 val)
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{
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writeb(val, priv->reg_base + port);
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}
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static void ems_pci_v2_post_irq(const struct sja1000_priv *priv)
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{
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struct ems_pci_card *card = (struct ems_pci_card *)priv->priv;
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writel(PLX_ICSR_ENA_CLR, card->conf_addr + PLX_ICSR);
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}
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/*
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@ -130,12 +166,12 @@ static inline int ems_pci_check_chan(const struct sja1000_priv *priv)
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unsigned char res;
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/* Make sure SJA1000 is in reset mode */
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ems_pci_write_reg(priv, REG_MOD, 1);
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priv->write_reg(priv, REG_MOD, 1);
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ems_pci_write_reg(priv, REG_CDR, CDR_PELICAN);
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priv->write_reg(priv, REG_CDR, CDR_PELICAN);
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/* read reset-values */
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res = ems_pci_read_reg(priv, REG_CDR);
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res = priv->read_reg(priv, REG_CDR);
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if (res == CDR_PELICAN)
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return 1;
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@ -188,6 +224,7 @@ static int __devinit ems_pci_add_card(struct pci_dev *pdev,
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struct sja1000_priv *priv;
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struct net_device *dev;
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struct ems_pci_card *card;
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int max_chan, mem_size, base_bar;
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int err, i;
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/* Enabling PCI device */
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@ -210,37 +247,52 @@ static int __devinit ems_pci_add_card(struct pci_dev *pdev,
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card->channels = 0;
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/* Remap PITA configuration space, and controller memory area */
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card->conf_addr = pci_iomap(pdev, 0, EMS_PCI_MEM_SIZE);
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if (pdev->vendor == PCI_VENDOR_ID_PLX) {
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card->version = 2; /* CPC-PCI v2 */
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max_chan = EMS_PCI_V2_MAX_CHAN;
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base_bar = EMS_PCI_V2_BASE_BAR;
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mem_size = EMS_PCI_V2_MEM_SIZE;
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} else {
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card->version = 1; /* CPC-PCI v1 */
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max_chan = EMS_PCI_V1_MAX_CHAN;
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base_bar = EMS_PCI_V1_BASE_BAR;
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mem_size = EMS_PCI_V1_MEM_SIZE;
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}
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/* Remap configuration space and controller memory area */
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card->conf_addr = pci_iomap(pdev, 0, mem_size);
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if (card->conf_addr == NULL) {
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err = -ENOMEM;
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goto failure_cleanup;
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}
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card->base_addr = pci_iomap(pdev, 1, EMS_PCI_MEM_SIZE);
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card->base_addr = pci_iomap(pdev, base_bar, mem_size);
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if (card->base_addr == NULL) {
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err = -ENOMEM;
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goto failure_cleanup;
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}
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if (card->version == 1) {
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/* Configure PITA-2 parallel interface (enable MUX) */
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writel(PITA2_MISC_CONFIG, card->conf_addr + PITA2_MISC);
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/* Check for unique EMS CAN signature */
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if (ems_pci_readb(card, 0) != 0x55 ||
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ems_pci_readb(card, 1) != 0xAA ||
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ems_pci_readb(card, 2) != 0x01 ||
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ems_pci_readb(card, 3) != 0xCB ||
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ems_pci_readb(card, 4) != 0x11) {
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dev_err(&pdev->dev, "Not EMS Dr. Thomas Wuensche interface\n");
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if (ems_pci_v1_readb(card, 0) != 0x55 ||
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ems_pci_v1_readb(card, 1) != 0xAA ||
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ems_pci_v1_readb(card, 2) != 0x01 ||
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ems_pci_v1_readb(card, 3) != 0xCB ||
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ems_pci_v1_readb(card, 4) != 0x11) {
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dev_err(&pdev->dev,
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"Not EMS Dr. Thomas Wuensche interface\n");
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err = -ENODEV;
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goto failure_cleanup;
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}
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}
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ems_pci_card_reset(card);
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/* Detect available channels */
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for (i = 0; i < EMS_PCI_MAX_CHAN; i++) {
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for (i = 0; i < max_chan; i++) {
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dev = alloc_sja1000dev(0);
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if (dev == NULL) {
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err = -ENOMEM;
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@ -255,20 +307,32 @@ static int __devinit ems_pci_add_card(struct pci_dev *pdev,
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dev->irq = pdev->irq;
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priv->reg_base = card->base_addr + EMS_PCI_CAN_BASE_OFFSET
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+ (i * EMS_PCI_CAN_CTRL_SIZE);
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if (card->version == 1) {
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priv->read_reg = ems_pci_v1_read_reg;
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priv->write_reg = ems_pci_v1_write_reg;
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priv->post_irq = ems_pci_v1_post_irq;
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} else {
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priv->read_reg = ems_pci_v2_read_reg;
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priv->write_reg = ems_pci_v2_write_reg;
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priv->post_irq = ems_pci_v2_post_irq;
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}
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/* Check if channel is present */
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if (ems_pci_check_chan(priv)) {
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priv->read_reg = ems_pci_read_reg;
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priv->write_reg = ems_pci_write_reg;
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priv->post_irq = ems_pci_post_irq;
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priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
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priv->ocr = EMS_PCI_OCR;
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priv->cdr = EMS_PCI_CDR;
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SET_NETDEV_DEV(dev, &pdev->dev);
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/* Enable interrupts from card */
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writel(PITA2_ICR_INT0_EN, card->conf_addr + PITA2_ICR);
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if (card->version == 1)
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/* reset int flag of pita */
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writel(PITA2_ICR_INT0_EN | PITA2_ICR_INT0,
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card->conf_addr + PITA2_ICR);
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else
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/* enable IRQ in PLX 9030 */
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writel(PLX_ICSR_ENA_CLR,
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card->conf_addr + PLX_ICSR);
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/* Register SJA1000 device */
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err = register_sja1000dev(dev);
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