mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 19:00:25 +00:00
Second Round of Renesas ARM Based SoC Updates for v3.14
* Global - Add select MIGHT_HAVE_PCI for PCI-AHB bridge code * r7s72100 SoC (RZ/A1H) - clks: remove duplicated clock from r7s72100 * R-Car Gen 2: r8a7791 (R-Car M2) and r8a7790 (R-Car H2) * Initialize CCF before clock sources * Do not setup timer in non-secure mode * r8a7791 (R-Car M2) - Conditionally select MICREL_PHY - Add clock index macros for DT sources - Add Ether clock * r8a7790 (R-Car H2) - Add clock index macros for DT sources - Add I2C support * r8a7778 (R-Car M1) - Add USB Func DMAEngine support - camera-rcar header cleanup - Add SSIx DMAEngine support * sh73a0 (SH-Mobile AG5) - Add FSI clock support for DT -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJSuQS2AAoJENfPZGlqN0++054P+wUVtv0JYmBzzb2A4HbsTyOw 4jjjNy3GKcOgYxd0OyNswwz1Dc3hdiKTRz66YR8qz1vondhHpo1trnSg5/WC4JG+ D5UHEgc5bkWqzddDEdOVZ/BWTT1bWfC3C8hf+8FQ9KOCbCsRUY5X3IoSEQ7ZanfX 09V1YNWXx+kynmtcXdBlm0jiPS2tFlXvX5U3fk5n0yRKCH6sGlKZS+syZzqO76As QrY4exNtTd+xbLlnHT2TGSwWk4fwBdOwTPyvcqg9BPY/OlRQ1+HK8n/N69qY8mRn DhuJU/Y9l0Ig89m1w39Wkn7r1w0ipTe9Nchf8F2gVhoNxnL+TPKwp+qc+zSNJvs1 DxgADw+5ehA3s7CSz4qYnz3dl4Ay3/mSUTnWYYqavIxPBOl5QTzMR32BJ9L9k6sh hPKdo5Me5aLglfpozqPVq76XQ5bT+HVQ8Auc4bt51r1sxvS65oeJqUo39I4yeMvw zaHxnWgzWqIDB3JlvYIezJtuz4tsnNIoDF37zKH7OVHS4EPXMr9Tg9JfghCc5seD xBGZPUXojMpLgHGR2wCR1WjGhXIFfVVwqeCtZq4GmV/9T+0MEen+vJu0/czvH0On XaNbRqU7uT+66tfd6QJIlR7ZBzoXIE4loCGEx1Zf5oEW5pcyrvCsB9hS9LngNlPp fm6FI4NodfYeuPuCURmI =rEpv -----END PGP SIGNATURE----- Merge tag 'renesas-soc2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Second Round of Renesas ARM Based SoC Updates for v3.14 * Global - Add select MIGHT_HAVE_PCI for PCI-AHB bridge code * r7s72100 SoC (RZ/A1H) - clks: remove duplicated clock from r7s72100 * R-Car Gen 2: r8a7791 (R-Car M2) and r8a7790 (R-Car H2) * Initialize CCF before clock sources * Do not setup timer in non-secure mode * r8a7791 (R-Car M2) - Conditionally select MICREL_PHY - Add clock index macros for DT sources - Add Ether clock * r8a7790 (R-Car H2) - Add clock index macros for DT sources - Add I2C support * r8a7778 (R-Car M1) - Add USB Func DMAEngine support - camera-rcar header cleanup - Add SSIx DMAEngine support * sh73a0 (SH-Mobile AG5) - Add FSI clock support for DT * tag 'renesas-soc2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm: shmobile: clks: remove duplicated clock from r7s72100 ARM: shmobile: koelsch: Conditionally select MICREL_PHY ARM: shmobile: rcar-gen2: Initialize CCF before clock sources ARM: shmobile: r8a7791: Add clock index macros for DT sources ARM: shmobile: r8a7790: Add clock index macros for DT sources ARM: shmobile: Add select MIGHT_HAVE_PCI for PCI-AHB bridge code ARM: shmobile: r8a7778: add USB Func DMAEngine support ARM: rcar-gen2: Do not setup timer in non-secure mode ARM: shmobile: r8a7791: add Ether clock ARM: shmobile: r8a7778: camera-rcar header cleanup ARM: shmobile: sh73a0: add FSI clock support for DT ARM: shmobile: r8a7790: add I2C support ARM: shmobile: r8a7778: add SSIx DMAEngine support Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
dd7d395883
12 changed files with 356 additions and 8 deletions
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@ -12,6 +12,7 @@ config ARCH_SHMOBILE_MULTI
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select HAVE_SMP
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select ARM_GIC
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select MIGHT_HAVE_CACHE_L2X0
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select MIGHT_HAVE_PCI
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select NO_IOPORT
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select PINCTRL
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select ARCH_REQUIRE_GPIOLIB
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@ -96,6 +97,7 @@ config ARCH_R8A7790
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARM_GIC
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select CPU_V7
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select MIGHT_HAVE_PCI
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select SH_CLK_CPG
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select RENESAS_IRQC
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@ -104,6 +106,7 @@ config ARCH_R8A7791
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARM_GIC
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select CPU_V7
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select MIGHT_HAVE_PCI
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select SH_CLK_CPG
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select RENESAS_IRQC
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@ -112,6 +115,7 @@ config ARCH_EMEV2
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARM_GIC
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select CPU_V7
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select MIGHT_HAVE_PCI
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select USE_OF
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select AUTO_ZRELADDR
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@ -239,6 +243,7 @@ config MACH_KOELSCH
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bool "Koelsch board"
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depends on ARCH_R8A7791
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select USE_OF
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select MICREL_PHY if SH_ETH
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config MACH_KZM9G
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bool "KZM-A9-GT board"
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@ -25,6 +25,7 @@
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#include <linux/mmc/sh_mmcif.h>
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#include <linux/mtd/partitions.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_data/camera-rcar.h>
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#include <linux/platform_data/usb-rcar-phy.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/fixed.h>
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@ -178,7 +178,6 @@ static struct clk_lookup lookups[] = {
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CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
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CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
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CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
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};
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void __init r7s72100_clock_init(void)
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@ -292,9 +292,13 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
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CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
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CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
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CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP931]),
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CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
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CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP930]),
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CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
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CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP929]),
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CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
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CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP928]),
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CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
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CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
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@ -122,6 +122,7 @@ static struct clk *main_clks[] = {
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/* MSTP */
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enum {
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MSTP813,
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MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
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MSTP719, MSTP718, MSTP715, MSTP714,
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MSTP522,
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@ -132,6 +133,7 @@ enum {
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
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[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
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[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
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[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
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@ -192,6 +194,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
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CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
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};
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#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
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@ -658,6 +658,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
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CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
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CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
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CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
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CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
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@ -20,13 +20,30 @@
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#define __ASM_R8A7778_H__
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#include <linux/sh_eth.h>
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#include <linux/platform_data/camera-rcar.h>
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/* HPB-DMA slave IDs */
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enum {
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HPBDMA_SLAVE_DUMMY,
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HPBDMA_SLAVE_SDHI0_TX,
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HPBDMA_SLAVE_SDHI0_RX,
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HPBDMA_SLAVE_SSI0_TX,
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HPBDMA_SLAVE_SSI0_RX,
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HPBDMA_SLAVE_SSI1_TX,
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HPBDMA_SLAVE_SSI1_RX,
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HPBDMA_SLAVE_SSI2_TX,
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HPBDMA_SLAVE_SSI2_RX,
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HPBDMA_SLAVE_SSI3_TX,
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HPBDMA_SLAVE_SSI3_RX,
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HPBDMA_SLAVE_SSI4_TX,
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HPBDMA_SLAVE_SSI4_RX,
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HPBDMA_SLAVE_SSI5_TX,
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HPBDMA_SLAVE_SSI5_RX,
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HPBDMA_SLAVE_SSI6_TX,
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HPBDMA_SLAVE_SSI6_RX,
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HPBDMA_SLAVE_SSI7_TX,
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HPBDMA_SLAVE_SSI7_RX,
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HPBDMA_SLAVE_SSI8_TX,
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HPBDMA_SLAVE_SSI8_RX,
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HPBDMA_SLAVE_HPBIF0_TX,
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HPBDMA_SLAVE_HPBIF0_RX,
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HPBDMA_SLAVE_HPBIF1_TX,
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@ -45,6 +62,8 @@ enum {
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HPBDMA_SLAVE_HPBIF7_RX,
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HPBDMA_SLAVE_HPBIF8_TX,
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HPBDMA_SLAVE_HPBIF8_RX,
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HPBDMA_SLAVE_USBFUNC_TX,
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HPBDMA_SLAVE_USBFUNC_RX,
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};
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extern void r8a7778_add_standard_devices(void);
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@ -319,6 +319,29 @@ void __init r8a7778_add_dt_devices(void)
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#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
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#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
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#define HPBDMA_SSI(_id) \
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{ \
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.id = HPBDMA_SLAVE_SSI## _id ##_TX, \
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.addr = 0xffd91008 + (_id * 0x40), \
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.dcr = HPB_DMAE_DCR_CT | \
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HPB_DMAE_DCR_DIP | \
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HPB_DMAE_DCR_SPDS_32BIT | \
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HPB_DMAE_DCR_DMDL | \
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HPB_DMAE_DCR_DPDS_32BIT, \
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.port = _id + (_id << 8), \
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.dma_ch = (28 + _id), \
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}, { \
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.id = HPBDMA_SLAVE_SSI## _id ##_RX, \
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.addr = 0xffd9100c + (_id * 0x40), \
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.dcr = HPB_DMAE_DCR_CT | \
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HPB_DMAE_DCR_DIP | \
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HPB_DMAE_DCR_SMDL | \
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HPB_DMAE_DCR_SPDS_32BIT | \
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HPB_DMAE_DCR_DPDS_32BIT, \
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.port = _id + (_id << 8), \
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.dma_ch = (28 + _id), \
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}
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#define HPBDMA_HPBIF(_id) \
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{ \
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.id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
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@ -371,8 +394,34 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
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.port = 0x0D0C,
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.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
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.dma_ch = 22,
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}, {
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.id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
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.addr = 0xffe60018,
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.dcr = HPB_DMAE_DCR_SPDS_32BIT |
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HPB_DMAE_DCR_DMDL |
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HPB_DMAE_DCR_DPDS_32BIT,
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.port = 0x0000,
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.dma_ch = 14,
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}, {
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.id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
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.addr = 0xffe6001c,
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.dcr = HPB_DMAE_DCR_SMDL |
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HPB_DMAE_DCR_SPDS_32BIT |
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HPB_DMAE_DCR_DPDS_32BIT,
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.port = 0x0101,
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.dma_ch = 15,
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},
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HPBDMA_SSI(0),
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HPBDMA_SSI(1),
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HPBDMA_SSI(2),
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HPBDMA_SSI(3),
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HPBDMA_SSI(4),
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HPBDMA_SSI(5),
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HPBDMA_SSI(6),
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HPBDMA_SSI(7),
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HPBDMA_SSI(8),
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HPBDMA_HPBIF(0),
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HPBDMA_HPBIF(1),
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HPBDMA_HPBIF(2),
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@ -385,24 +434,44 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
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};
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static const struct hpb_dmae_channel hpb_dmae_channels[] = {
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HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
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HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
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HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
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HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
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HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
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};
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@ -63,6 +63,27 @@ R8A7790_GPIO(5);
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&r8a7790_gpio##idx##_platform_data, \
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sizeof(r8a7790_gpio##idx##_platform_data))
|
||||
|
||||
static struct resource i2c_resources[] __initdata = {
|
||||
/* I2C0 */
|
||||
DEFINE_RES_MEM(0xE6508000, 0x40),
|
||||
DEFINE_RES_IRQ(gic_spi(287)),
|
||||
/* I2C1 */
|
||||
DEFINE_RES_MEM(0xE6518000, 0x40),
|
||||
DEFINE_RES_IRQ(gic_spi(288)),
|
||||
/* I2C2 */
|
||||
DEFINE_RES_MEM(0xE6530000, 0x40),
|
||||
DEFINE_RES_IRQ(gic_spi(286)),
|
||||
/* I2C3 */
|
||||
DEFINE_RES_MEM(0xE6540000, 0x40),
|
||||
DEFINE_RES_IRQ(gic_spi(290)),
|
||||
|
||||
};
|
||||
|
||||
#define r8a7790_register_i2c(idx) \
|
||||
platform_device_register_simple( \
|
||||
"i2c-rcar", idx, \
|
||||
i2c_resources + (2 * idx), 2); \
|
||||
|
||||
void __init r8a7790_pinmux_init(void)
|
||||
{
|
||||
platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
|
||||
|
@ -73,6 +94,10 @@ void __init r8a7790_pinmux_init(void)
|
|||
r8a7790_register_gpio(3);
|
||||
r8a7790_register_gpio(4);
|
||||
r8a7790_register_gpio(5);
|
||||
r8a7790_register_i2c(0);
|
||||
r8a7790_register_i2c(1);
|
||||
r8a7790_register_i2c(2);
|
||||
r8a7790_register_i2c(3);
|
||||
}
|
||||
|
||||
#define SCIF_COMMON(scif_type, baseaddr, irq) \
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/clk/shmobile.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
|
@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void)
|
|||
|
||||
void __init rcar_gen2_timer_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER
|
||||
#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
|
||||
u32 mode = rcar_gen2_read_mode_pins();
|
||||
#endif
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER
|
||||
void __iomem *base;
|
||||
int extal_mhz = 0;
|
||||
u32 freq;
|
||||
|
@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void)
|
|||
/* Remap "armgcnt address map" space */
|
||||
base = ioremap(0xe6080000, PAGE_SIZE);
|
||||
|
||||
/* Update registers with correct frequency */
|
||||
iowrite32(freq, base + CNTFID0);
|
||||
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
|
||||
/*
|
||||
* Update the timer if it is either not running, or is not at the
|
||||
* right frequency. The timer is only configurable in secure mode
|
||||
* so this avoids an abort if the loader started the timer and
|
||||
* entered the kernel in non-secure mode.
|
||||
*/
|
||||
|
||||
if ((ioread32(base + CNTCR) & 1) == 0 ||
|
||||
ioread32(base + CNTFID0) != freq) {
|
||||
/* Update registers with correct frequency */
|
||||
iowrite32(freq, base + CNTFID0);
|
||||
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
|
||||
|
||||
/* make sure arch timer is started by setting bit 0 of CNTCR */
|
||||
iowrite32(1, base + CNTCR);
|
||||
}
|
||||
|
||||
/* make sure arch timer is started by setting bit 0 of CNTCR */
|
||||
iowrite32(1, base + CNTCR);
|
||||
iounmap(base);
|
||||
#endif /* CONFIG_ARM_ARCH_TIMER */
|
||||
|
||||
#ifdef CONFIG_COMMON_CLK
|
||||
rcar_gen2_clocks_init(mode);
|
||||
#endif
|
||||
clocksource_of_init();
|
||||
}
|
||||
|
|
100
include/dt-bindings/clock/r8a7790-clock.h
Normal file
100
include/dt-bindings/clock/r8a7790-clock.h
Normal file
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7790_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7790_CLK_MAIN 0
|
||||
#define R8A7790_CLK_PLL0 1
|
||||
#define R8A7790_CLK_PLL1 2
|
||||
#define R8A7790_CLK_PLL3 3
|
||||
#define R8A7790_CLK_LB 4
|
||||
#define R8A7790_CLK_QSPI 5
|
||||
#define R8A7790_CLK_SDH 6
|
||||
#define R8A7790_CLK_SD0 7
|
||||
#define R8A7790_CLK_SD1 8
|
||||
#define R8A7790_CLK_Z 9
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7790_CLK_TMU1 11
|
||||
#define R8A7790_CLK_TMU3 21
|
||||
#define R8A7790_CLK_TMU2 22
|
||||
#define R8A7790_CLK_CMT0 24
|
||||
#define R8A7790_CLK_TMU0 25
|
||||
#define R8A7790_CLK_VSP1_DU1 27
|
||||
#define R8A7790_CLK_VSP1_DU0 28
|
||||
#define R8A7790_CLK_VSP1_RT 30
|
||||
#define R8A7790_CLK_VSP1_SY 31
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7790_CLK_SCIFA2 2
|
||||
#define R8A7790_CLK_SCIFA1 3
|
||||
#define R8A7790_CLK_SCIFA0 4
|
||||
#define R8A7790_CLK_SCIFB0 6
|
||||
#define R8A7790_CLK_SCIFB1 7
|
||||
#define R8A7790_CLK_SCIFB2 16
|
||||
#define R8A7790_CLK_SYS_DMAC0 18
|
||||
#define R8A7790_CLK_SYS_DMAC1 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7790_CLK_TPU0 4
|
||||
#define R8A7790_CLK_MMCIF1 5
|
||||
#define R8A7790_CLK_SDHI3 11
|
||||
#define R8A7790_CLK_SDHI2 12
|
||||
#define R8A7790_CLK_SDHI1 13
|
||||
#define R8A7790_CLK_SDHI0 14
|
||||
#define R8A7790_CLK_MMCIF0 15
|
||||
#define R8A7790_CLK_SSUSB 28
|
||||
#define R8A7790_CLK_CMT1 29
|
||||
#define R8A7790_CLK_USBDMAC0 30
|
||||
#define R8A7790_CLK_USBDMAC1 31
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7790_CLK_THERMAL 22
|
||||
#define R8A7790_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7790_CLK_EHCI 3
|
||||
#define R8A7790_CLK_HSUSB 4
|
||||
#define R8A7790_CLK_HSCIF1 16
|
||||
#define R8A7790_CLK_HSCIF0 17
|
||||
#define R8A7790_CLK_SCIF1 20
|
||||
#define R8A7790_CLK_SCIF0 21
|
||||
#define R8A7790_CLK_DU2 22
|
||||
#define R8A7790_CLK_DU1 23
|
||||
#define R8A7790_CLK_DU0 24
|
||||
#define R8A7790_CLK_LVDS1 25
|
||||
#define R8A7790_CLK_LVDS0 26
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7790_CLK_VIN3 8
|
||||
#define R8A7790_CLK_VIN2 9
|
||||
#define R8A7790_CLK_VIN1 10
|
||||
#define R8A7790_CLK_VIN0 11
|
||||
#define R8A7790_CLK_ETHER 13
|
||||
#define R8A7790_CLK_SATA1 14
|
||||
#define R8A7790_CLK_SATA0 15
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7790_CLK_GPIO5 7
|
||||
#define R8A7790_CLK_GPIO4 8
|
||||
#define R8A7790_CLK_GPIO3 9
|
||||
#define R8A7790_CLK_GPIO2 10
|
||||
#define R8A7790_CLK_GPIO1 11
|
||||
#define R8A7790_CLK_GPIO0 12
|
||||
#define R8A7790_CLK_RCAN1 15
|
||||
#define R8A7790_CLK_RCAN0 16
|
||||
#define R8A7790_CLK_IICDVFS 26
|
||||
#define R8A7790_CLK_I2C3 28
|
||||
#define R8A7790_CLK_I2C2 29
|
||||
#define R8A7790_CLK_I2C1 30
|
||||
#define R8A7790_CLK_I2C0 31
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
|
105
include/dt-bindings/clock/r8a7791-clock.h
Normal file
105
include/dt-bindings/clock/r8a7791-clock.h
Normal file
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7791_H__
|
||||
|
||||
/* CPG */
|
||||
#define R8A7791_CLK_MAIN 0
|
||||
#define R8A7791_CLK_PLL0 1
|
||||
#define R8A7791_CLK_PLL1 2
|
||||
#define R8A7791_CLK_PLL3 3
|
||||
#define R8A7791_CLK_LB 4
|
||||
#define R8A7791_CLK_QSPI 5
|
||||
#define R8A7791_CLK_SDH 6
|
||||
#define R8A7791_CLK_SD0 7
|
||||
#define R8A7791_CLK_Z 8
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7791_CLK_TMU1 11
|
||||
#define R8A7791_CLK_TMU3 21
|
||||
#define R8A7791_CLK_TMU2 22
|
||||
#define R8A7791_CLK_CMT0 24
|
||||
#define R8A7791_CLK_TMU0 25
|
||||
#define R8A7791_CLK_VSP1_DU1 27
|
||||
#define R8A7791_CLK_VSP1_DU0 28
|
||||
#define R8A7791_CLK_VSP1_SY 31
|
||||
|
||||
/* MSTP2 */
|
||||
#define R8A7791_CLK_SCIFA2 2
|
||||
#define R8A7791_CLK_SCIFA1 3
|
||||
#define R8A7791_CLK_SCIFA0 4
|
||||
#define R8A7791_CLK_SCIFB0 6
|
||||
#define R8A7791_CLK_SCIFB1 7
|
||||
#define R8A7791_CLK_SCIFB2 16
|
||||
#define R8A7791_CLK_DMAC 18
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7791_CLK_TPU0 4
|
||||
#define R8A7791_CLK_SDHI2 11
|
||||
#define R8A7791_CLK_SDHI1 12
|
||||
#define R8A7791_CLK_SDHI0 14
|
||||
#define R8A7791_CLK_MMCIF0 15
|
||||
#define R8A7791_CLK_SSUSB 28
|
||||
#define R8A7791_CLK_CMT1 29
|
||||
#define R8A7791_CLK_USBDMAC0 30
|
||||
#define R8A7791_CLK_USBDMAC1 31
|
||||
|
||||
/* MSTP5 */
|
||||
#define R8A7791_CLK_THERMAL 22
|
||||
#define R8A7791_CLK_PWM 23
|
||||
|
||||
/* MSTP7 */
|
||||
#define R8A7791_CLK_HSUSB 4
|
||||
#define R8A7791_CLK_HSCIF2 13
|
||||
#define R8A7791_CLK_SCIF5 14
|
||||
#define R8A7791_CLK_SCIF4 15
|
||||
#define R8A7791_CLK_HSCIF1 16
|
||||
#define R8A7791_CLK_HSCIF0 17
|
||||
#define R8A7791_CLK_SCIF3 18
|
||||
#define R8A7791_CLK_SCIF2 19
|
||||
#define R8A7791_CLK_SCIF1 20
|
||||
#define R8A7791_CLK_SCIF0 21
|
||||
#define R8A7791_CLK_DU1 23
|
||||
#define R8A7791_CLK_DU0 24
|
||||
#define R8A7791_CLK_LVDS0 26
|
||||
|
||||
/* MSTP8 */
|
||||
#define R8A7791_CLK_VIN2 9
|
||||
#define R8A7791_CLK_VIN1 10
|
||||
#define R8A7791_CLK_VIN0 11
|
||||
#define R8A7791_CLK_ETHER 13
|
||||
#define R8A7791_CLK_SATA1 14
|
||||
#define R8A7791_CLK_SATA0 15
|
||||
|
||||
/* MSTP9 */
|
||||
#define R8A7791_CLK_GPIO7 4
|
||||
#define R8A7791_CLK_GPIO6 5
|
||||
#define R8A7791_CLK_GPIO5 7
|
||||
#define R8A7791_CLK_GPIO4 8
|
||||
#define R8A7791_CLK_GPIO3 9
|
||||
#define R8A7791_CLK_GPIO2 10
|
||||
#define R8A7791_CLK_GPIO1 11
|
||||
#define R8A7791_CLK_GPIO0 12
|
||||
#define R8A7791_CLK_RCAN1 15
|
||||
#define R8A7791_CLK_RCAN0 16
|
||||
#define R8A7791_CLK_I2C5 25
|
||||
#define R8A7791_CLK_IICDVFS 26
|
||||
#define R8A7791_CLK_I2C4 27
|
||||
#define R8A7791_CLK_I2C3 28
|
||||
#define R8A7791_CLK_I2C2 29
|
||||
#define R8A7791_CLK_I2C1 30
|
||||
#define R8A7791_CLK_I2C0 31
|
||||
|
||||
/* MSTP11 */
|
||||
#define R8A7791_CLK_SCIFA3 6
|
||||
#define R8A7791_CLK_SCIFA4 7
|
||||
#define R8A7791_CLK_SCIFA5 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
|
Loading…
Reference in a new issue