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drm/i915: don't enable self-refresh on Ironlake
We don't know how to enable it safely, especially as outputs turn on and off. When disabling LP1 we also need to make sure LP2 and 3 are already disabled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29173 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29082 Reported-by: Chris Lord <chris@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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2 changed files with 12 additions and 2 deletions
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@ -2206,9 +2206,17 @@
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#define WM1_LP_SR_EN (1<<31)
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#define WM1_LP_LATENCY_SHIFT 24
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#define WM1_LP_LATENCY_MASK (0x7f<<24)
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#define WM1_LP_FBC_LP1_MASK (0xf<<20)
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#define WM1_LP_FBC_LP1_SHIFT 20
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#define WM1_LP_SR_MASK (0x1ff<<8)
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#define WM1_LP_SR_SHIFT 8
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#define WM1_LP_CURSOR_MASK (0x3f)
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#define WM2_LP_ILK 0x4510c
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#define WM2_LP_EN (1<<31)
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#define WM3_LP_ILK 0x45110
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#define WM3_LP_EN (1<<31)
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#define WM1S_LP_ILK 0x45120
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#define WM1S_LP_EN (1<<31)
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/* Memory latency timer register */
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#define MLTR_ILK 0x11222
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@ -3382,8 +3382,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
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reg_value = I915_READ(WM1_LP_ILK);
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reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
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WM1_LP_CURSOR_MASK);
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reg_value |= WM1_LP_SR_EN |
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(ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
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reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
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(sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
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I915_WRITE(WM1_LP_ILK, reg_value);
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@ -5669,6 +5668,9 @@ void intel_init_clock_gating(struct drm_device *dev)
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I915_WRITE(DISP_ARB_CTL,
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(I915_READ(DISP_ARB_CTL) |
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DISP_FBC_WM_DIS));
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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}
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/*
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* Based on the document from hardware guys the following bits
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