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crypto: cast5-avx - tune assembler code for more performance
Patch replaces 'movb' instructions with 'movzbl' to break false register
dependencies, interleaves instructions better for out-of-order scheduling
and merges constant 16-bit rotation with round-key variable rotation.
tcrypt ECB results (128bit key):
Intel Core i5-2450M:
size old-vs-new new-vs-generic old-vs-generic
enc dec enc dec enc dec
256 1.18x 1.18x 2.45x 2.47x 2.08x 2.10x
1k 1.20x 1.20x 2.73x 2.73x 2.28x 2.28x
8k 1.20x 1.19x 2.73x 2.73x 2.28x 2.29x
[v2]
- Do instruction interleaving another way to avoid adding new FPU<=>CPU
register moves as these cause performance drop on Bulldozer.
- Improvements to round-key variable rotation handling.
- Further interleaving improvements for better out-of-order scheduling.
Cc: Johannes Goetzfried <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Jussi Kivilinna
Herbert Xu
parent
f94a73f8dd
commit
ddaea7869d
1 changed files with 160 additions and 106 deletions
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@ -4,6 +4,8 @@
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* Copyright (C) 2012 Johannes Goetzfried
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* Copyright (C) 2012 Johannes Goetzfried
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* <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
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* <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
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*
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*
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* Copyright © 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* the Free Software Foundation; either version 2 of the License, or
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@ -22,7 +24,6 @@
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*/
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*/
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.file "cast5-avx-x86_64-asm_64.S"
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.file "cast5-avx-x86_64-asm_64.S"
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.text
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.extern cast5_s1
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.extern cast5_s1
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.extern cast5_s2
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.extern cast5_s2
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@ -57,17 +58,19 @@
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#define RX %xmm8
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#define RX %xmm8
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#define RKM %xmm9
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#define RKM %xmm9
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#define RKRF %xmm10
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#define RKR %xmm10
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#define RKRR %xmm11
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#define RKRF %xmm11
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#define RKRR %xmm12
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#define RTMP %xmm12
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#define R32 %xmm13
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#define RMASK %xmm13
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#define R1ST %xmm14
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#define R32 %xmm14
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#define RID1 %rax
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#define RTMP %xmm15
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#define RID1b %al
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#define RID2 %rbx
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#define RID1 %rbp
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#define RID2b %bl
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#define RID1d %ebp
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#define RID2 %rsi
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#define RID2d %esi
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#define RGI1 %rdx
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#define RGI1 %rdx
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#define RGI1bl %dl
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#define RGI1bl %dl
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@ -76,6 +79,13 @@
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#define RGI2bl %cl
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#define RGI2bl %cl
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#define RGI2bh %ch
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#define RGI2bh %ch
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#define RGI3 %rax
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#define RGI3bl %al
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#define RGI3bh %ah
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#define RGI4 %rbx
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#define RGI4bl %bl
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#define RGI4bh %bh
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#define RFS1 %r8
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#define RFS1 %r8
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#define RFS1d %r8d
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#define RFS1d %r8d
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#define RFS2 %r9
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#define RFS2 %r9
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@ -84,60 +94,84 @@
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#define RFS3d %r10d
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#define RFS3d %r10d
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#define lookup_32bit(src, dst, op1, op2, op3) \
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#define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \
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movb src ## bl, RID1b; \
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movzbl src ## bh, RID1d; \
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movb src ## bh, RID2b; \
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movzbl src ## bl, RID2d; \
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shrq $16, src; \
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movl s1(, RID1, 4), dst ## d; \
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movl s1(, RID1, 4), dst ## d; \
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op1 s2(, RID2, 4), dst ## d; \
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op1 s2(, RID2, 4), dst ## d; \
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shrq $16, src; \
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movzbl src ## bh, RID1d; \
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movb src ## bl, RID1b; \
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movzbl src ## bl, RID2d; \
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movb src ## bh, RID2b; \
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interleave_op(il_reg); \
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op2 s3(, RID1, 4), dst ## d; \
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op2 s3(, RID1, 4), dst ## d; \
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op3 s4(, RID2, 4), dst ## d;
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op3 s4(, RID2, 4), dst ## d;
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#define F(a, x, op0, op1, op2, op3) \
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#define dummy(d) /* do nothing */
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#define shr_next(reg) \
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shrq $16, reg;
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#define F_head(a, x, gi1, gi2, op0) \
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op0 a, RKM, x; \
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op0 a, RKM, x; \
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vpslld RKRF, x, RTMP; \
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vpslld RKRF, x, RTMP; \
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vpsrld RKRR, x, x; \
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vpsrld RKRR, x, x; \
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vpor RTMP, x, x; \
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vpor RTMP, x, x; \
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\
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\
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vpshufb RMASK, x, x; \
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vmovq x, gi1; \
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vmovq x, RGI1; \
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vpextrq $1, x, gi2;
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vpsrldq $8, x, x; \
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vmovq x, RGI2; \
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#define F_tail(a, x, gi1, gi2, op1, op2, op3) \
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lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \
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lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \
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\
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\
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lookup_32bit(RGI1, RFS1, op1, op2, op3); \
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lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \
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shrq $16, RGI1; \
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shlq $32, RFS2; \
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lookup_32bit(RGI1, RFS2, op1, op2, op3); \
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orq RFS1, RFS2; \
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shlq $32, RFS2; \
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lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \
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orq RFS1, RFS2; \
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shlq $32, RFS1; \
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orq RFS1, RFS3; \
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\
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\
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lookup_32bit(RGI2, RFS1, op1, op2, op3); \
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vmovq RFS2, x; \
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shrq $16, RGI2; \
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lookup_32bit(RGI2, RFS3, op1, op2, op3); \
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shlq $32, RFS3; \
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orq RFS1, RFS3; \
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\
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vmovq RFS2, x; \
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vpinsrq $1, RFS3, x, x;
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vpinsrq $1, RFS3, x, x;
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#define F1(b, x) F(b, x, vpaddd, xorl, subl, addl)
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#define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \
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#define F2(b, x) F(b, x, vpxor, subl, addl, xorl)
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F_head(b1, RX, RGI1, RGI2, op0); \
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#define F3(b, x) F(b, x, vpsubd, addl, xorl, subl)
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F_head(b2, RX, RGI3, RGI4, op0); \
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\
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F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
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F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
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\
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vpxor a1, RX, a1; \
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vpxor a2, RTMP, a2;
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#define subround(a, b, x, n, f) \
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#define F1_2(a1, b1, a2, b2) \
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F ## f(b, x); \
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F_2(a1, b1, a2, b2, vpaddd, xorl, subl, addl)
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vpxor a, x, a;
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#define F2_2(a1, b1, a2, b2) \
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F_2(a1, b1, a2, b2, vpxor, subl, addl, xorl)
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#define F3_2(a1, b1, a2, b2) \
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F_2(a1, b1, a2, b2, vpsubd, addl, xorl, subl)
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#define subround(a1, b1, a2, b2, f) \
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F ## f ## _2(a1, b1, a2, b2);
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#define round(l, r, n, f) \
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#define round(l, r, n, f) \
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vbroadcastss (km+(4*n))(CTX), RKM; \
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vbroadcastss (km+(4*n))(CTX), RKM; \
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vpinsrb $0, (kr+n)(CTX), RKRF, RKRF; \
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vpand R1ST, RKR, RKRF; \
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vpsubq RKRF, R32, RKRR; \
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vpsubq RKRF, R32, RKRR; \
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subround(l ## 1, r ## 1, RX, n, f); \
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vpsrldq $1, RKR, RKR; \
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subround(l ## 2, r ## 2, RX, n, f); \
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subround(l ## 1, r ## 1, l ## 2, r ## 2, f); \
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subround(l ## 3, r ## 3, RX, n, f); \
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subround(l ## 3, r ## 3, l ## 4, r ## 4, f);
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subround(l ## 4, r ## 4, RX, n, f);
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#define enc_preload_rkr() \
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vbroadcastss .L16_mask, RKR; \
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/* add 16-bit rotation to key rotations (mod 32) */ \
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vpxor kr(CTX), RKR, RKR;
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#define dec_preload_rkr() \
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vbroadcastss .L16_mask, RKR; \
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/* add 16-bit rotation to key rotations (mod 32) */ \
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vpxor kr(CTX), RKR, RKR; \
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vpshufb .Lbswap128_mask, RKR, RKR;
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#define transpose_2x4(x0, x1, t0, t1) \
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#define transpose_2x4(x0, x1, t0, t1) \
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vpunpckldq x1, x0, t0; \
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vpunpckldq x1, x0, t0; \
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@ -146,37 +180,47 @@
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vpunpcklqdq t1, t0, x0; \
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vpunpcklqdq t1, t0, x0; \
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vpunpckhqdq t1, t0, x1;
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vpunpckhqdq t1, t0, x1;
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#define inpack_blocks(in, x0, x1, t0, t1) \
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#define inpack_blocks(in, x0, x1, t0, t1, rmask) \
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vmovdqu (0*4*4)(in), x0; \
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vmovdqu (0*4*4)(in), x0; \
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vmovdqu (1*4*4)(in), x1; \
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vmovdqu (1*4*4)(in), x1; \
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vpshufb RMASK, x0, x0; \
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vpshufb rmask, x0, x0; \
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vpshufb RMASK, x1, x1; \
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vpshufb rmask, x1, x1; \
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\
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\
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transpose_2x4(x0, x1, t0, t1)
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transpose_2x4(x0, x1, t0, t1)
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#define outunpack_blocks(out, x0, x1, t0, t1) \
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#define outunpack_blocks(out, x0, x1, t0, t1, rmask) \
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transpose_2x4(x0, x1, t0, t1) \
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transpose_2x4(x0, x1, t0, t1) \
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\
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\
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vpshufb RMASK, x0, x0; \
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vpshufb rmask, x0, x0; \
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vpshufb RMASK, x1, x1; \
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vpshufb rmask, x1, x1; \
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vmovdqu x0, (0*4*4)(out); \
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vmovdqu x0, (0*4*4)(out); \
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vmovdqu x1, (1*4*4)(out);
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vmovdqu x1, (1*4*4)(out);
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#define outunpack_xor_blocks(out, x0, x1, t0, t1) \
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#define outunpack_xor_blocks(out, x0, x1, t0, t1, rmask) \
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transpose_2x4(x0, x1, t0, t1) \
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transpose_2x4(x0, x1, t0, t1) \
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\
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\
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vpshufb RMASK, x0, x0; \
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vpshufb rmask, x0, x0; \
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vpshufb RMASK, x1, x1; \
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vpshufb rmask, x1, x1; \
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vpxor (0*4*4)(out), x0, x0; \
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vpxor (0*4*4)(out), x0, x0; \
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vmovdqu x0, (0*4*4)(out); \
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vmovdqu x0, (0*4*4)(out); \
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vpxor (1*4*4)(out), x1, x1; \
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vpxor (1*4*4)(out), x1, x1; \
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vmovdqu x1, (1*4*4)(out);
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vmovdqu x1, (1*4*4)(out);
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.data
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.align 16
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.align 16
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.Lbswap_mask:
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.Lbswap_mask:
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.byte 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12
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.byte 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12
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.Lbswap128_mask:
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.byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
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.L16_mask:
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.byte 16, 16, 16, 16
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.L32_mask:
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.L32_mask:
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.byte 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ,0, 0, 0, 0, 0
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.byte 32, 0, 0, 0
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.Lfirst_mask:
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.byte 0x1f, 0, 0, 0
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.text
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.align 16
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.align 16
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.global __cast5_enc_blk_16way
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.global __cast5_enc_blk_16way
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@ -190,23 +234,24 @@ __cast5_enc_blk_16way:
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* %rcx: bool, if true: xor output
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* %rcx: bool, if true: xor output
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*/
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*/
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pushq %rbp;
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pushq %rbx;
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pushq %rbx;
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pushq %rcx;
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pushq %rcx;
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vmovdqu .Lbswap_mask, RMASK;
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vmovdqa .Lbswap_mask, RKM;
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vmovdqu .L32_mask, R32;
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vmovd .Lfirst_mask, R1ST;
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vpxor RKRF, RKRF, RKRF;
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vmovd .L32_mask, R32;
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enc_preload_rkr();
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inpack_blocks(%rdx, RL1, RR1, RTMP, RX);
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leaq 1*(2*4*4)(%rdx), %rax;
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leaq (2*4*4)(%rdx), %rax;
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inpack_blocks(%rdx, RL1, RR1, RTMP, RX, RKM);
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inpack_blocks(%rax, RL2, RR2, RTMP, RX);
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inpack_blocks(%rax, RL2, RR2, RTMP, RX, RKM);
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leaq (2*4*4)(%rax), %rax;
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leaq 2*(2*4*4)(%rdx), %rax;
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inpack_blocks(%rax, RL3, RR3, RTMP, RX);
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inpack_blocks(%rax, RL3, RR3, RTMP, RX, RKM);
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leaq (2*4*4)(%rax), %rax;
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leaq 3*(2*4*4)(%rdx), %rax;
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inpack_blocks(%rax, RL4, RR4, RTMP, RX);
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inpack_blocks(%rax, RL4, RR4, RTMP, RX, RKM);
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xorq RID1, RID1;
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movq %rsi, %r11;
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xorq RID2, RID2;
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round(RL, RR, 0, 1);
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round(RL, RR, 0, 1);
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round(RR, RL, 1, 2);
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round(RR, RL, 1, 2);
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@ -221,8 +266,8 @@ __cast5_enc_blk_16way:
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round(RL, RR, 10, 2);
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round(RL, RR, 10, 2);
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round(RR, RL, 11, 3);
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round(RR, RL, 11, 3);
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movb rr(CTX), %al;
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movzbl rr(CTX), %eax;
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testb %al, %al;
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testl %eax, %eax;
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jnz __skip_enc;
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jnz __skip_enc;
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round(RL, RR, 12, 1);
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round(RL, RR, 12, 1);
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@ -233,28 +278,30 @@ __cast5_enc_blk_16way:
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__skip_enc:
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__skip_enc:
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popq %rcx;
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popq %rcx;
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popq %rbx;
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popq %rbx;
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popq %rbp;
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vmovdqa .Lbswap_mask, RKM;
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leaq 1*(2*4*4)(%r11), %rax;
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testb %cl, %cl;
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testb %cl, %cl;
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jnz __enc_xor16;
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jnz __enc_xor16;
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outunpack_blocks(%rsi, RR1, RL1, RTMP, RX);
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outunpack_blocks(%r11, RR1, RL1, RTMP, RX, RKM);
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leaq (2*4*4)(%rsi), %rax;
|
outunpack_blocks(%rax, RR2, RL2, RTMP, RX, RKM);
|
||||||
outunpack_blocks(%rax, RR2, RL2, RTMP, RX);
|
leaq 2*(2*4*4)(%r11), %rax;
|
||||||
leaq (2*4*4)(%rax), %rax;
|
outunpack_blocks(%rax, RR3, RL3, RTMP, RX, RKM);
|
||||||
outunpack_blocks(%rax, RR3, RL3, RTMP, RX);
|
leaq 3*(2*4*4)(%r11), %rax;
|
||||||
leaq (2*4*4)(%rax), %rax;
|
outunpack_blocks(%rax, RR4, RL4, RTMP, RX, RKM);
|
||||||
outunpack_blocks(%rax, RR4, RL4, RTMP, RX);
|
|
||||||
|
|
||||||
ret;
|
ret;
|
||||||
|
|
||||||
__enc_xor16:
|
__enc_xor16:
|
||||||
outunpack_xor_blocks(%rsi, RR1, RL1, RTMP, RX);
|
outunpack_xor_blocks(%r11, RR1, RL1, RTMP, RX, RKM);
|
||||||
leaq (2*4*4)(%rsi), %rax;
|
outunpack_xor_blocks(%rax, RR2, RL2, RTMP, RX, RKM);
|
||||||
outunpack_xor_blocks(%rax, RR2, RL2, RTMP, RX);
|
leaq 2*(2*4*4)(%r11), %rax;
|
||||||
leaq (2*4*4)(%rax), %rax;
|
outunpack_xor_blocks(%rax, RR3, RL3, RTMP, RX, RKM);
|
||||||
outunpack_xor_blocks(%rax, RR3, RL3, RTMP, RX);
|
leaq 3*(2*4*4)(%r11), %rax;
|
||||||
leaq (2*4*4)(%rax), %rax;
|
outunpack_xor_blocks(%rax, RR4, RL4, RTMP, RX, RKM);
|
||||||
outunpack_xor_blocks(%rax, RR4, RL4, RTMP, RX);
|
|
||||||
|
|
||||||
ret;
|
ret;
|
||||||
|
|
||||||
|
|
@ -269,25 +316,26 @@ cast5_dec_blk_16way:
|
||||||
* %rdx: src
|
* %rdx: src
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
pushq %rbp;
|
||||||
pushq %rbx;
|
pushq %rbx;
|
||||||
|
|
||||||
vmovdqu .Lbswap_mask, RMASK;
|
vmovdqa .Lbswap_mask, RKM;
|
||||||
vmovdqu .L32_mask, R32;
|
vmovd .Lfirst_mask, R1ST;
|
||||||
vpxor RKRF, RKRF, RKRF;
|
vmovd .L32_mask, R32;
|
||||||
|
dec_preload_rkr();
|
||||||
|
|
||||||
inpack_blocks(%rdx, RL1, RR1, RTMP, RX);
|
leaq 1*(2*4*4)(%rdx), %rax;
|
||||||
leaq (2*4*4)(%rdx), %rax;
|
inpack_blocks(%rdx, RL1, RR1, RTMP, RX, RKM);
|
||||||
inpack_blocks(%rax, RL2, RR2, RTMP, RX);
|
inpack_blocks(%rax, RL2, RR2, RTMP, RX, RKM);
|
||||||
leaq (2*4*4)(%rax), %rax;
|
leaq 2*(2*4*4)(%rdx), %rax;
|
||||||
inpack_blocks(%rax, RL3, RR3, RTMP, RX);
|
inpack_blocks(%rax, RL3, RR3, RTMP, RX, RKM);
|
||||||
leaq (2*4*4)(%rax), %rax;
|
leaq 3*(2*4*4)(%rdx), %rax;
|
||||||
inpack_blocks(%rax, RL4, RR4, RTMP, RX);
|
inpack_blocks(%rax, RL4, RR4, RTMP, RX, RKM);
|
||||||
|
|
||||||
xorq RID1, RID1;
|
movq %rsi, %r11;
|
||||||
xorq RID2, RID2;
|
|
||||||
|
|
||||||
movb rr(CTX), %al;
|
movzbl rr(CTX), %eax;
|
||||||
testb %al, %al;
|
testl %eax, %eax;
|
||||||
jnz __skip_dec;
|
jnz __skip_dec;
|
||||||
|
|
||||||
round(RL, RR, 15, 1);
|
round(RL, RR, 15, 1);
|
||||||
|
|
@ -295,7 +343,7 @@ cast5_dec_blk_16way:
|
||||||
round(RL, RR, 13, 2);
|
round(RL, RR, 13, 2);
|
||||||
round(RR, RL, 12, 1);
|
round(RR, RL, 12, 1);
|
||||||
|
|
||||||
__skip_dec:
|
__dec_tail:
|
||||||
round(RL, RR, 11, 3);
|
round(RL, RR, 11, 3);
|
||||||
round(RR, RL, 10, 2);
|
round(RR, RL, 10, 2);
|
||||||
round(RL, RR, 9, 1);
|
round(RL, RR, 9, 1);
|
||||||
|
|
@ -309,14 +357,20 @@ __skip_dec:
|
||||||
round(RL, RR, 1, 2);
|
round(RL, RR, 1, 2);
|
||||||
round(RR, RL, 0, 1);
|
round(RR, RL, 0, 1);
|
||||||
|
|
||||||
|
vmovdqa .Lbswap_mask, RKM;
|
||||||
popq %rbx;
|
popq %rbx;
|
||||||
|
popq %rbp;
|
||||||
|
|
||||||
outunpack_blocks(%rsi, RR1, RL1, RTMP, RX);
|
leaq 1*(2*4*4)(%r11), %rax;
|
||||||
leaq (2*4*4)(%rsi), %rax;
|
outunpack_blocks(%r11, RR1, RL1, RTMP, RX, RKM);
|
||||||
outunpack_blocks(%rax, RR2, RL2, RTMP, RX);
|
outunpack_blocks(%rax, RR2, RL2, RTMP, RX, RKM);
|
||||||
leaq (2*4*4)(%rax), %rax;
|
leaq 2*(2*4*4)(%r11), %rax;
|
||||||
outunpack_blocks(%rax, RR3, RL3, RTMP, RX);
|
outunpack_blocks(%rax, RR3, RL3, RTMP, RX, RKM);
|
||||||
leaq (2*4*4)(%rax), %rax;
|
leaq 3*(2*4*4)(%r11), %rax;
|
||||||
outunpack_blocks(%rax, RR4, RL4, RTMP, RX);
|
outunpack_blocks(%rax, RR4, RL4, RTMP, RX, RKM);
|
||||||
|
|
||||||
ret;
|
ret;
|
||||||
|
|
||||||
|
__skip_dec:
|
||||||
|
vpsrldq $4, RKR, RKR;
|
||||||
|
jmp __dec_tail;
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue