mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
radeon: add support for vblank on crtc2
This adds support for CRTC2 vblank on radeon similiar to the i915. Signed-off-by: Dave Airlie <airlied@linux.ie>
This commit is contained in:
parent
7c158acef8
commit
ddbee33328
6 changed files with 124 additions and 14 deletions
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@ -1420,6 +1420,10 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
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return DRM_ERR(EINVAL);
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}
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/* Enable vblank on CRTC1 for older X servers
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*/
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dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
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switch(init->func) {
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case RADEON_INIT_R200_CP:
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dev_priv->microcode_version = UCODE_R200;
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@ -655,6 +655,7 @@ typedef struct drm_radeon_indirect {
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#define RADEON_PARAM_GART_TEX_HANDLE 10
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#define RADEON_PARAM_SCRATCH_OFFSET 11
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#define RADEON_PARAM_CARD_TYPE 12
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#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
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typedef struct drm_radeon_getparam {
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int param;
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@ -708,7 +709,7 @@ typedef struct drm_radeon_setparam {
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#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
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#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
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#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
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#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
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/* 1.14: Clients can allocate/free a surface
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*/
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typedef struct drm_radeon_surface_alloc {
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@ -721,4 +722,7 @@ typedef struct drm_radeon_surface_free {
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unsigned int address;
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} drm_radeon_surface_free_t;
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#define DRM_RADEON_VBLANK_CRTC1 1
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#define DRM_RADEON_VBLANK_CRTC2 2
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#endif
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@ -60,7 +60,7 @@ static struct drm_driver driver = {
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.driver_features =
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DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
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DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED |
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DRIVER_IRQ_VBL,
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DRIVER_IRQ_VBL | DRIVER_IRQ_VBL2,
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.dev_priv_size = sizeof(drm_radeon_buf_priv_t),
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.load = radeon_driver_load,
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.firstopen = radeon_driver_firstopen,
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@ -70,6 +70,7 @@ static struct drm_driver driver = {
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.lastclose = radeon_driver_lastclose,
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.unload = radeon_driver_unload,
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.vblank_wait = radeon_driver_vblank_wait,
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.vblank_wait2 = radeon_driver_vblank_wait2,
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.dri_library_name = dri_library_name,
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.irq_preinstall = radeon_driver_irq_preinstall,
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.irq_postinstall = radeon_driver_irq_postinstall,
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@ -97,9 +97,10 @@
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* new packet type)
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* 1.26- Add support for variable size PCI(E) gart aperture
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* 1.27- Add support for IGP GART
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* 1.28- Add support for VBL on CRTC2
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*/
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 27
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#define DRIVER_MINOR 28
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#define DRIVER_PATCHLEVEL 0
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/*
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@ -277,6 +278,9 @@ typedef struct drm_radeon_private {
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/* SW interrupt */
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wait_queue_head_t swi_queue;
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atomic_t swi_emitted;
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int vblank_crtc;
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uint32_t irq_enable_reg;
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int irq_enabled;
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struct radeon_surface surfaces[RADEON_MAX_SURFACES];
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struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
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@ -356,10 +360,14 @@ extern int radeon_irq_wait(DRM_IOCTL_ARGS);
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extern void radeon_do_release(drm_device_t * dev);
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extern int radeon_driver_vblank_wait(drm_device_t * dev,
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unsigned int *sequence);
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extern int radeon_driver_vblank_wait2(drm_device_t * dev,
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unsigned int *sequence);
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extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
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extern void radeon_driver_irq_preinstall(drm_device_t * dev);
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extern void radeon_driver_irq_postinstall(drm_device_t * dev);
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extern void radeon_driver_irq_uninstall(drm_device_t * dev);
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extern int radeon_vblank_crtc_get(drm_device_t *dev);
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extern int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value);
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extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
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extern int radeon_driver_unload(struct drm_device *dev);
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@ -496,12 +504,15 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
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#define RADEON_GEN_INT_CNTL 0x0040
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# define RADEON_CRTC_VBLANK_MASK (1 << 0)
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# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
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# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
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# define RADEON_SW_INT_ENABLE (1 << 25)
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#define RADEON_GEN_INT_STATUS 0x0044
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# define RADEON_CRTC_VBLANK_STAT (1 << 0)
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# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
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# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
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# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
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# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
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# define RADEON_SW_INT_TEST (1 << 25)
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# define RADEON_SW_INT_TEST_ACK (1 << 25)
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@ -73,18 +73,35 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
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* outside the DRM
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*/
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stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
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RADEON_CRTC_VBLANK_STAT));
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RADEON_CRTC_VBLANK_STAT |
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RADEON_CRTC2_VBLANK_STAT));
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if (!stat)
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return IRQ_NONE;
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stat &= dev_priv->irq_enable_reg;
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/* SW interrupt */
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if (stat & RADEON_SW_INT_TEST) {
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DRM_WAKEUP(&dev_priv->swi_queue);
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}
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/* VBLANK interrupt */
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if (stat & RADEON_CRTC_VBLANK_STAT) {
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atomic_inc(&dev->vbl_received);
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if (stat & (RADEON_CRTC_VBLANK_STAT|RADEON_CRTC2_VBLANK_STAT)) {
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int vblank_crtc = dev_priv->vblank_crtc;
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if ((vblank_crtc &
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(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
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(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
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if (stat & RADEON_CRTC_VBLANK_STAT)
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atomic_inc(&dev->vbl_received);
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if (stat & RADEON_CRTC2_VBLANK_STAT)
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atomic_inc(&dev->vbl_received2);
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} else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
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(vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
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((stat & RADEON_CRTC2_VBLANK_STAT) &&
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(vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
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atomic_inc(&dev->vbl_received);
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DRM_WAKEUP(&dev->vbl_queue);
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drm_vbl_send_signals(dev);
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}
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@ -127,19 +144,30 @@ static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
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return ret;
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}
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int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
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int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
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int crtc)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *) dev->dev_private;
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unsigned int cur_vblank;
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int ret = 0;
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int ack = 0;
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atomic_t *counter;
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if (!dev_priv) {
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DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
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return DRM_ERR(EINVAL);
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}
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radeon_acknowledge_irqs(dev_priv, RADEON_CRTC_VBLANK_STAT);
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if (crtc == DRM_RADEON_VBLANK_CRTC1) {
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counter = &dev->vbl_received;
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ack |= RADEON_CRTC_VBLANK_STAT;
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} else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
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counter = &dev->vbl_received2;
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ack |= RADEON_CRTC2_VBLANK_STAT;
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} else
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return DRM_ERR(EINVAL);
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radeon_acknowledge_irqs(dev_priv, ack);
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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@ -148,7 +176,7 @@ int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
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* using vertical blanks...
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*/
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DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
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(((cur_vblank = atomic_read(&dev->vbl_received))
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(((cur_vblank = atomic_read(counter))
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- *sequence) <= (1 << 23)));
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*sequence = cur_vblank;
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@ -156,6 +184,16 @@ int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
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return ret;
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}
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int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
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{
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return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
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}
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int radeon_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
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{
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return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
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}
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/* Needs the lock as it touches the ring.
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*/
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int radeon_irq_emit(DRM_IOCTL_ARGS)
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@ -204,6 +242,21 @@ int radeon_irq_wait(DRM_IOCTL_ARGS)
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return radeon_wait_irq(dev, irqwait.irq_seq);
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}
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static void radeon_enable_interrupt(drm_device_t *dev)
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{
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drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
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dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
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if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
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dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
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if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
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dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
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RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
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dev_priv->irq_enabled = 1;
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}
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/* drm_dma.h hooks
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*/
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void radeon_driver_irq_preinstall(drm_device_t * dev)
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@ -216,7 +269,8 @@ void radeon_driver_irq_preinstall(drm_device_t * dev)
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/* Clear bits if they're already high */
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radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
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RADEON_CRTC_VBLANK_STAT));
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RADEON_CRTC_VBLANK_STAT |
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RADEON_CRTC2_VBLANK_STAT));
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}
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void radeon_driver_irq_postinstall(drm_device_t * dev)
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@ -227,9 +281,7 @@ void radeon_driver_irq_postinstall(drm_device_t * dev)
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atomic_set(&dev_priv->swi_emitted, 0);
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DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
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/* Turn on SW and VBL ints */
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RADEON_WRITE(RADEON_GEN_INT_CNTL,
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RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE);
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radeon_enable_interrupt(dev);
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}
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void radeon_driver_irq_uninstall(drm_device_t * dev)
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@ -239,6 +291,38 @@ void radeon_driver_irq_uninstall(drm_device_t * dev)
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if (!dev_priv)
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return;
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dev_priv->irq_enabled = 0;
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/* Disable *all* interrupts */
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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}
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int radeon_vblank_crtc_get(drm_device_t *dev)
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{
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drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
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u32 flag;
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u32 value;
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flag = RADEON_READ(RADEON_GEN_INT_CNTL);
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value = 0;
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if (flag & RADEON_CRTC_VBLANK_MASK)
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value |= DRM_RADEON_VBLANK_CRTC1;
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if (flag & RADEON_CRTC2_VBLANK_MASK)
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value |= DRM_RADEON_VBLANK_CRTC2;
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return value;
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}
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int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
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{
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drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
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if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
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DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
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return DRM_ERR(EINVAL);
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}
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dev_priv->vblank_crtc = (unsigned int)value;
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radeon_enable_interrupt(dev);
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return 0;
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}
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@ -3085,6 +3085,9 @@ static int radeon_cp_getparam(DRM_IOCTL_ARGS)
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else
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value = RADEON_CARD_PCI;
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break;
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case RADEON_PARAM_VBLANK_CRTC:
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value = radeon_vblank_crtc_get(dev);
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break;
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default:
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DRM_DEBUG("Invalid parameter %d\n", param.param);
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return DRM_ERR(EINVAL);
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@ -3141,6 +3144,9 @@ static int radeon_cp_setparam(DRM_IOCTL_ARGS)
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if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
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dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
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break;
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case RADEON_SETPARAM_VBLANK_CRTC:
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return radeon_vblank_crtc_set(dev, sp.value);
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break;
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default:
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DRM_DEBUG("Invalid parameter %d\n", sp.param);
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return DRM_ERR(EINVAL);
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