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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] use bcd2bin/bin2bcd [IA64] Ensure cpu0 can access per-cpu variables in early boot code
This commit is contained in:
commit
ddc752a406
7 changed files with 54 additions and 13 deletions
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@ -236,7 +236,7 @@ extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
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extern unsigned short sal_revision; /* supported SAL spec revision */
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extern unsigned short sal_version; /* SAL version; OEM dependent */
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#define SAL_VERSION_CODE(major, minor) ((BIN2BCD(major) << 8) | BIN2BCD(minor))
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#define SAL_VERSION_CODE(major, minor) ((bin2bcd(major) << 8) | bin2bcd(minor))
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extern const char *ia64_sal_strerror (long status);
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extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
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@ -359,7 +359,31 @@ start_ap:
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mov ar.rsc=0 // place RSE in enforced lazy mode
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;;
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loadrs // clear the dirty partition
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mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
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movl r19=__phys_per_cpu_start
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mov r18=PERCPU_PAGE_SIZE
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;;
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#ifndef CONFIG_SMP
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add r19=r19,r18
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;;
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#else
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(isAP) br.few 2f
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mov r20=r19
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sub r19=r19,r18
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;;
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shr.u r18=r18,3
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1:
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ld8 r21=[r20],8;;
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st8[r19]=r21,8
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adds r18=-1,r18;;
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cmp4.lt p7,p6=0,r18
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(p7) br.cond.dptk.few 1b
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2:
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#endif
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tpa r19=r19
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;;
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.pred.rel.mutex isBP,isAP
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(isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
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(isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
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;;
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mov ar.bspstore=r2 // establish the new RSE stack
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;;
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@ -927,16 +927,18 @@ cpu_init (void)
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if (smp_processor_id() == 0) {
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cpu_set(0, per_cpu(cpu_sibling_map, 0));
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cpu_set(0, cpu_core_map[0]);
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}
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#endif
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} else {
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/*
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* We set ar.k3 so that assembly code in MCA handler can compute
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* Set ar.k3 so that assembly code in MCA handler can compute
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* physical addresses of per cpu variables with a simple:
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* phys = ar.k3 + &per_cpu_var
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* and the alt-dtlb-miss handler can set per-cpu mapping into
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* the TLB when needed. head.S already did this for cpu0.
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*/
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ia64_set_kr(IA64_KR_PER_CPU_DATA,
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ia64_tpa(cpu_data) - (long) __per_cpu_start);
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}
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#endif
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get_max_cacheline_size();
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@ -467,7 +467,9 @@ start_secondary (void *unused)
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{
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/* Early console may use I/O ports */
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ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
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#ifndef CONFIG_PRINTK_TIME
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Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
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#endif
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efi_map_pal_code();
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cpu_init();
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preempt_disable();
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@ -215,6 +215,9 @@ SECTIONS
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/* Per-cpu data: */
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percpu : { } :percpu
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. = ALIGN(PERCPU_PAGE_SIZE);
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#ifdef CONFIG_SMP
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. = . + PERCPU_PAGE_SIZE; /* cpu0 per-cpu space */
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#endif
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__phys_per_cpu_start = .;
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.data.percpu PERCPU_ADDR : AT(__phys_per_cpu_start - LOAD_OFFSET)
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{
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@ -163,8 +163,14 @@ per_cpu_init (void)
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* get_zeroed_page().
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*/
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if (first_time) {
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void *cpu0_data = __phys_per_cpu_start - PERCPU_PAGE_SIZE;
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first_time=0;
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for (cpu = 0; cpu < NR_CPUS; cpu++) {
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__per_cpu_offset[0] = (char *) cpu0_data - __per_cpu_start;
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per_cpu(local_per_cpu_offset, 0) = __per_cpu_offset[0];
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for (cpu = 1; cpu < NR_CPUS; cpu++) {
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memcpy(cpu_data, __phys_per_cpu_start, __per_cpu_end - __per_cpu_start);
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__per_cpu_offset[cpu] = (char *) cpu_data - __per_cpu_start;
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cpu_data += PERCPU_PAGE_SIZE;
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@ -177,7 +183,7 @@ per_cpu_init (void)
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static inline void
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alloc_per_cpu_data(void)
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{
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cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * NR_CPUS,
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cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * NR_CPUS-1,
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PERCPU_PAGE_SIZE, __pa(MAX_DMA_ADDRESS));
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}
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#else
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@ -143,7 +143,11 @@ static void *per_cpu_node_setup(void *cpu_data, int node)
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int cpu;
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for_each_possible_early_cpu(cpu) {
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if (node == node_cpuid[cpu].nid) {
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if (cpu == 0) {
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void *cpu0_data = __phys_per_cpu_start - PERCPU_PAGE_SIZE;
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__per_cpu_offset[cpu] = (char*)cpu0_data -
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__per_cpu_start;
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} else if (node == node_cpuid[cpu].nid) {
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memcpy(__va(cpu_data), __phys_per_cpu_start,
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__per_cpu_end - __per_cpu_start);
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__per_cpu_offset[cpu] = (char*)__va(cpu_data) -
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