ARM: DT: Hisilicon ARMv7 SoC Hi3519 DT updates for 4.8
- Add device tree bindings for hi3519 sysctrl - Add dts files for hi3519 - Tidy up DTB makefile entries to keep the list sorted -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXfMdXAAoJEAvIV27ZiWZcS0UP/R1ihe0zFwK1SGZDAjIBZyhe Zq7sk/VhjPiD3ewtbjNQkAmRaSTtF+gii3t40FEPjNZL/skLhMFLEKyUAAhiipqG 8OMF+PnooC6kOXB/RnMCxggWK2lOwbuaXsOHv0Ux7wWqP+sLWQzji3hgIk7hJsXx Y9ZYCMBuDgEqPwldpK6E8+jmpPoqktC7MpahWjk+t6fVIPFX+QIm2uUM4BvGI61P tcEe59v4OSKcm/QC50bhPmYVikk9R8Mt3gCL5Qjh4rFHtRyKzyJiPy7HdkJMDf6R pACKnF8qwyT2Qr1V5qn7M2Xygqwfh20tq9mcBcLLR1qlZHjdzxWNxT706elX9pWp D9DDQQdbe22gejq8nDYCBttXiFrzRdSOG5Vx2dTdGxfFXog93tADSvgScwI8Gon+ frPXbJaqWeLR6K5QhM/jUcj0/9kPAE2B0c/fP89I6IFIcOm0EbB7hJaDzudQb2Vz ewEigYqpamEhqBiOFMpgl60/HbMyAWpJ2869YpzFITO6XXRGMxiPc31ShLrziQmJ fcuAlVfixmM8tBdmdMVFN8U8bRnwY+KSChWO9J00ehnDeNOnqc8JsvNTppHo7h2U XklSru6iLB9TxTk6Ld8oPPJTaNKO0HdmATpJrCM10oCk67TYWs25v24cYnSyRBrk AxmKI8yNwpznX9/cNPYD =7zT7 -----END PGP SIGNATURE----- Merge tag 'hisi-armv7-soc-dt-for-4.8-v2' of git://github.com/hisilicon/linux-hisi into next/dt Merge "ARM: DT: Hisilicon ARMv7 SoC Hi3519 DT updates for 4.8" from Wei Xu: - Add device tree bindings for hi3519 sysctrl - Add dts files for hi3519 - Tidy up DTB makefile entries to keep the list sorted * tag 'hisi-armv7-soc-dt-for-4.8-v2' of git://github.com/hisilicon/linux-hisi: ARM: dts: add dts files for Hi3519 and tidy up the makefile entries ARM: dt-bindings: add device tree bindings for Hi3519 sysctrl
This commit is contained in:
Arnd Bergmann
commit
dddaea6b96
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@ -0,0 +1,14 @@
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* Hisilicon Hi3519 System Controller Block
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This bindings use the following binding:
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Documentation/devicetree/bindings/mfd/syscon.txt
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Required properties:
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- compatible: "hisilicon,hi3519-sysctrl".
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- reg: the register region of this block
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Examples:
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sysctrl: system-controller@12010000 {
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compatible = "hisilicon,hi3519-sysctrl", "syscon";
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reg = <0x12010000 0x1000>;
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};
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@ -154,8 +154,6 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
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exynos5800-peach-pi.dtb
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dtb-$(CONFIG_ARCH_HI3xxx) += \
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hi3620-hi4511.dtb
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dtb-$(CONFIG_ARCH_HIX5HD2) += \
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hisi-x5hd2-dkb.dtb
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dtb-$(CONFIG_ARCH_HIGHBANK) += \
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highbank.dtb \
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ecx-2000.dtb
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@ -163,6 +161,10 @@ dtb-$(CONFIG_ARCH_HIP01) += \
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hip01-ca9x2.dtb
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dtb-$(CONFIG_ARCH_HIP04) += \
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hip04-d01.dtb
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dtb-$(CONFIG_ARCH_HISI) += \
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hi3519-demb.dtb
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dtb-$(CONFIG_ARCH_HIX5HD2) += \
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hisi-x5hd2-dkb.dtb
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dtb-$(CONFIG_ARCH_INTEGRATOR) += \
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integratorap.dtb \
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integratorcp.dtb
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/dts-v1/;
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#include "hi3519.dtsi"
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/ {
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model = "HiSilicon HI3519 DEMO Board";
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compatible = "hisilicon,hi3519";
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aliases {
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serial0 = &uart0;
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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&dual_timer0 {
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status = "okay";
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};
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@ -0,0 +1,187 @@
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/*
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* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <dt-bindings/clock/hi3519-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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};
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};
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gic: interrupt-controller@10300000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
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};
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clk_3m: clk_3m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <3000000>;
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};
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crg: clock-reset-controller@12010000 {
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compatible = "hisilicon,hi3519-crg";
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#clock-cells = <1>;
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#reset-cells = <2>;
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reg = <0x12010000 0x10000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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uart0: serial@12100000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12100000 0x1000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART0_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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uart1: serial@12101000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12101000 0x1000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART1_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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uart2: serial@12102000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12102000 0x1000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART2_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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uart3: serial@12103000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12103000 0x1000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART3_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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uart4: serial@12104000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12104000 0x1000>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_UART4_CLK>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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dual_timer0: timer@12000000 {
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compatible = "arm,sp804", "arm,primecell";
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x12000000 0x1000>;
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clocks = <&clk_3m>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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dual_timer1: timer@12001000 {
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compatible = "arm,sp804", "arm,primecell";
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x12001000 0x1000>;
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clocks = <&clk_3m>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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dual_timer2: timer@12002000 {
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compatible = "arm,sp804", "arm,primecell";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x12002000 0x1000>;
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clocks = <&clk_3m>;
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clock-names = "apb_pclk";
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status = "disable";
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};
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spi_bus0: spi@12120000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x12120000 0x1000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_SPI0_CLK>;
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clock-names = "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disable";
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};
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spi_bus1: spi@12121000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x12121000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_SPI1_CLK>;
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clock-names = "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disable";
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};
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spi_bus2: spi@12122000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x12122000 0x1000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HI3519_SPI2_CLK>;
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clock-names = "apb_pclk";
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disable";
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};
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sysctrl: system-controller@12020000 {
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compatible = "hisilicon,hi3519-sysctrl", "syscon";
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reg = <0x12020000 0x1000>;
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&sysctrl>;
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offset = <0x4>;
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mask = <0xdeadbeef>;
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};
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};
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};
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