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arm64: dts: qcom: sa8775p: add USB nodes
Add nodes for the USB and it's PHY on sa8775p platform. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230428130824.23803-6-quic_shazhuss@quicinc.com
This commit is contained in:
Shazad Hussain
Bjorn Andersson
parent
09b701b89a
commit
de1001525c
1 changed files with 237 additions and 2 deletions
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@ -455,8 +455,8 @@ gcc: clock-controller@100000 {
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<&usb_0_qmpphy>,
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<&usb_1_qmpphy>,
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<0>,
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<0>,
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<0>,
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@ -649,6 +649,241 @@ ufs_mem_phy: phy@1d87000 {
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status = "disabled";
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};
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usb_0_hsphy: phy@88e4000 {
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compatible = "qcom,sa8775p-usb-hs-phy",
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"qcom,usb-snps-hs-5nm-phy";
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reg = <0 0x088e4000 0 0x120>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref";
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resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_0_qmpphy: phy@88e8000 {
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compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
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reg = <0 0x088e8000 0 0x2000>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&gcc GCC_USB_CLKREF_EN>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "aux", "ref", "com_aux", "pipe";
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resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
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<&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
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reset-names = "phy", "phy_phy";
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power-domains = <&gcc USB30_PRIM_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "usb3_prim_phy_pipe_clk_src";
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_0: usb@a6f8800 {
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compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
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reg = <0 0x0a6f8800 0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
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clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 14 IRQ_TYPE_EDGE_RISING>,
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<&pdc 15 IRQ_TYPE_EDGE_RISING>,
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<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq",
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"ss_phy_irq";
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power-domains = <&gcc USB30_PRIM_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
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interconnect-names = "usb-ddr", "apps-usb";
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wakeup-source;
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status = "disabled";
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usb_0_dwc3: usb@a600000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a600000 0 0xe000>;
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interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x080 0x0>;
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phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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usb_1_hsphy: phy@88e6000 {
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compatible = "qcom,sa8775p-usb-hs-phy",
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"qcom,usb-snps-hs-5nm-phy";
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reg = <0 0x088e6000 0 0x120>;
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clocks = <&gcc GCC_USB_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_1_qmpphy: phy@88ea000 {
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compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
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reg = <0 0x088ea000 0 0x2000>;
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clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
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<&gcc GCC_USB_CLKREF_EN>,
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<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
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clock-names = "aux", "ref", "com_aux", "pipe";
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resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
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<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
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reset-names = "phy", "phy_phy";
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power-domains = <&gcc USB30_SEC_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "usb3_sec_phy_pipe_clk_src";
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_1: usb@a8f8800 {
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compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
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reg = <0 0x0a8f8800 0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
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<&gcc GCC_USB30_SEC_SLEEP_CLK>,
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<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
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clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
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assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SEC_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 8 IRQ_TYPE_EDGE_RISING>,
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<&pdc 7 IRQ_TYPE_EDGE_RISING>,
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<&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq",
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"ss_phy_irq";
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power-domains = <&gcc USB30_SEC_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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resets = <&gcc GCC_USB30_SEC_BCR>;
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interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
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interconnect-names = "usb-ddr", "apps-usb";
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wakeup-source;
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status = "disabled";
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usb_1_dwc3: usb@a800000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a800000 0 0xe000>;
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interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x0a0 0x0>;
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phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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usb_2_hsphy: phy@88e7000 {
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compatible = "qcom,sa8775p-usb-hs-phy",
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"qcom,usb-snps-hs-5nm-phy";
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reg = <0 0x088e7000 0 0x120>;
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clocks = <&gcc GCC_USB_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_2: usb@a4f8800 {
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compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
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reg = <0 0x0a4f8800 0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_USB20_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
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<&gcc GCC_USB20_SLEEP_CLK>,
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<&gcc GCC_USB20_MOCK_UTMI_CLK>;
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clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
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assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
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<&gcc GCC_USB20_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 10 IRQ_TYPE_EDGE_RISING>,
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<&pdc 9 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "pwr_event",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq";
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power-domains = <&gcc USB20_PRIM_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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resets = <&gcc GCC_USB20_PRIM_BCR>;
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interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
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interconnect-names = "usb-ddr", "apps-usb";
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wakeup-source;
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status = "disabled";
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usb_2_dwc3: usb@a400000 {
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compatible = "snps,dwc3";
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reg = <0 0x0a400000 0 0xe000>;
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interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x020 0x0>;
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phys = <&usb_2_hsphy>;
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phy-names = "usb2-phy";
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};
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x0 0x01f40000 0x0 0x20000>;
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