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davinci: make clock rate re-calculation easy
Make clock rate recalculation easy by having a re-calculate function for each clock. The existing functions for calculation of output rates of PLL and PLL-derived sysclks have been convered to the new re-calculate API. A new function is introduced to take care of rate (re)calculation for leaf clocks. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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parent
f02bf3b396
commit
de381a91f5
2 changed files with 50 additions and 20 deletions
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@ -135,8 +135,12 @@ int clk_register(struct clk *clk)
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if (clk->rate)
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return 0;
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/* Else, see if there is a way to calculate it */
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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/* Otherwise, default to parent rate */
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if (clk->parent)
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else if (clk->parent)
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clk->rate = clk->parent->rate;
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return 0;
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@ -184,50 +188,62 @@ static int __init clk_disable_unused(void)
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late_initcall(clk_disable_unused);
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#endif
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static void clk_sysclk_recalc(struct clk *clk)
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static unsigned long clk_sysclk_recalc(struct clk *clk)
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{
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u32 v, plldiv;
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struct pll_data *pll;
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unsigned long rate = clk->rate;
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/* If this is the PLL base clock, no more calculations needed */
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if (clk->pll_data)
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return;
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return rate;
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if (WARN_ON(!clk->parent))
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return;
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return rate;
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clk->rate = clk->parent->rate;
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rate = clk->parent->rate;
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/* Otherwise, the parent must be a PLL */
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if (WARN_ON(!clk->parent->pll_data))
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return;
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return rate;
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pll = clk->parent->pll_data;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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clk->rate = pll->input_rate;
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rate = pll->input_rate;
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if (!clk->div_reg)
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return;
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return rate;
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v = __raw_readl(pll->base + clk->div_reg);
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if (v & PLLDIV_EN) {
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plldiv = (v & PLLDIV_RATIO_MASK) + 1;
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if (plldiv)
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clk->rate /= plldiv;
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rate /= plldiv;
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}
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return rate;
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}
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static void __init clk_pll_init(struct clk *clk)
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static unsigned long clk_leafclk_recalc(struct clk *clk)
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{
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if (WARN_ON(!clk->parent))
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return clk->rate;
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return clk->parent->rate;
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}
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static unsigned long clk_pllclk_recalc(struct clk *clk)
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{
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u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
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u8 bypass;
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struct pll_data *pll = clk->pll_data;
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unsigned long rate = clk->rate;
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pll->base = IO_ADDRESS(pll->phys_base);
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ctrl = __raw_readl(pll->base + PLLCTL);
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clk->rate = pll->input_rate = clk->parent->rate;
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rate = pll->input_rate = clk->parent->rate;
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if (ctrl & PLLCTL_PLLEN) {
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bypass = 0;
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@ -260,9 +276,9 @@ static void __init clk_pll_init(struct clk *clk)
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}
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if (!bypass) {
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clk->rate /= prediv;
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clk->rate *= mult;
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clk->rate /= postdiv;
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rate /= prediv;
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rate *= mult;
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rate /= postdiv;
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}
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pr_debug("PLL%d: input = %lu MHz [ ",
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@ -275,7 +291,9 @@ static void __init clk_pll_init(struct clk *clk)
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pr_debug("* %d ", mult);
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if (postdiv > 1)
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pr_debug("/ %d ", postdiv);
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pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
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pr_debug("] --> %lu MHz output.\n", rate / 1000000);
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return rate;
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}
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int __init davinci_clk_init(struct davinci_clk *clocks)
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@ -286,12 +304,23 @@ int __init davinci_clk_init(struct davinci_clk *clocks)
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for (c = clocks; c->lk.clk; c++) {
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clk = c->lk.clk;
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if (clk->pll_data)
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clk_pll_init(clk);
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if (!clk->recalc) {
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/* Calculate rates for PLL-derived clocks */
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else if (clk->flags & CLK_PLL)
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clk_sysclk_recalc(clk);
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/* Check if clock is a PLL */
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if (clk->pll_data)
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clk->recalc = clk_pllclk_recalc;
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/* Else, if it is a PLL-derived clock */
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else if (clk->flags & CLK_PLL)
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clk->recalc = clk_sysclk_recalc;
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/* Otherwise, it is a leaf clock (PSC clock) */
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else if (clk->parent)
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clk->recalc = clk_leafclk_recalc;
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}
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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if (clk->lpsc)
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clk->flags |= CLK_PSC;
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@ -73,6 +73,7 @@ struct clk {
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struct list_head childnode; /* parent's child list node */
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struct pll_data *pll_data;
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u32 div_reg;
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unsigned long (*recalc) (struct clk *);
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};
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/* Clock flags */
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