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drm/i915: Initialize CHV digital lock detect threshold
Initialize lock detect threshold and select coarse threshold for the case where M2 fraction division is disabled. v2: Split the changes into multiple smaller patches (Ville) v3: Clear out the old bits before we modify those bits as RMW (Ville) v4: Reset coarse threshold when M2 fraction is enabled (Ville) Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com> Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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2 changed files with 10 additions and 0 deletions
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@ -1046,6 +1046,7 @@ enum skl_disp_power_wells {
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#define _CHV_PLL_DW9_CH0 0x8024
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#define _CHV_PLL_DW9_CH1 0x81A4
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#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
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#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
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#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
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#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
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@ -6207,6 +6207,15 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
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dpio_val |= DPIO_CHV_FRAC_DIV_EN;
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vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
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/* Program digital lock detect threshold */
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dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
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dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
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DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
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dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
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if (!bestm2_frac)
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dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
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vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
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/* Loop filter */
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refclk = i9xx_get_refclk(crtc, 0);
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loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
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