mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-07 11:28:32 +00:00
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: amd64_edac: check NB MCE bank enable on the current node properly amd64_edac: Rewrite unganged mode code of f10_early_channel_count amd64_edac: cleanup amd64_check_ecc_enabled x86, EDAC: Provide function to return NodeId of a CPU amd64_edac: build driver only on AMD hardware
This commit is contained in:
commit
de55a8958f
5 changed files with 88 additions and 103 deletions
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@ -1020,4 +1020,6 @@ extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
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extern int get_tsc_mode(unsigned long adr);
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extern int set_tsc_mode(unsigned int val);
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extern int amd_get_nb_id(int cpu);
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#endif /* _ASM_X86_PROCESSOR_H */
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@ -333,6 +333,16 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
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#endif
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}
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int amd_get_nb_id(int cpu)
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{
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int id = 0;
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#ifdef CONFIG_SMP
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id = per_cpu(cpu_llc_id, cpu);
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#endif
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return id;
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}
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EXPORT_SYMBOL_GPL(amd_get_nb_id);
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static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
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{
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#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
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@ -59,7 +59,7 @@ config EDAC_MM_EDAC
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
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depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI
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depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && CPU_SUP_AMD
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help
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Support for error detection and correction on the AMD 64
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Families of Memory Controllers (K8, F10h and F11h)
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@ -1255,7 +1255,9 @@ static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map)
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*/
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static int f10_early_channel_count(struct amd64_pvt *pvt)
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{
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int dbams[] = { DBAM0, DBAM1 };
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int err = 0, channels = 0;
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int i, j;
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u32 dbam;
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err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0);
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@ -1288,46 +1290,19 @@ static int f10_early_channel_count(struct amd64_pvt *pvt)
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* is more than just one DIMM present in unganged mode. Need to check
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* both controllers since DIMMs can be placed in either one.
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*/
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channels = 0;
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err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM0, &dbam);
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if (err)
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goto err_reg;
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if (DBAM_DIMM(0, dbam) > 0)
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channels++;
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if (DBAM_DIMM(1, dbam) > 0)
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channels++;
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if (DBAM_DIMM(2, dbam) > 0)
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channels++;
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if (DBAM_DIMM(3, dbam) > 0)
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channels++;
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/* If more than 2 DIMMs are present, then we have 2 channels */
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if (channels > 2)
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channels = 2;
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else if (channels == 0) {
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/* No DIMMs on DCT0, so look at DCT1 */
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err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM1, &dbam);
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for (i = 0; i < ARRAY_SIZE(dbams); i++) {
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err = pci_read_config_dword(pvt->dram_f2_ctl, dbams[i], &dbam);
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if (err)
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goto err_reg;
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if (DBAM_DIMM(0, dbam) > 0)
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channels++;
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if (DBAM_DIMM(1, dbam) > 0)
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channels++;
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if (DBAM_DIMM(2, dbam) > 0)
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channels++;
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if (DBAM_DIMM(3, dbam) > 0)
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channels++;
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if (channels > 2)
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channels = 2;
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for (j = 0; j < 4; j++) {
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if (DBAM_DIMM(j, dbam) > 0) {
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channels++;
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break;
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}
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}
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}
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/* If we found ALL 0 values, then assume just ONE DIMM-ONE Channel */
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if (channels == 0)
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channels = 1;
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debugf0("MCT channel count: %d\n", channels);
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return channels;
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@ -2766,30 +2741,53 @@ static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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}
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static void check_mcg_ctl(void *ret)
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/* get all cores on this DCT */
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static void get_cpus_on_this_dct_cpumask(cpumask_t *mask, int nid)
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{
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u64 msr_val = 0;
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u8 nbe;
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int cpu;
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rdmsrl(MSR_IA32_MCG_CTL, msr_val);
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nbe = msr_val & K8_MSR_MCGCTL_NBE;
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debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
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raw_smp_processor_id(), msr_val,
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(nbe ? "enabled" : "disabled"));
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if (!nbe)
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*(int *)ret = 0;
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for_each_online_cpu(cpu)
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if (amd_get_nb_id(cpu) == nid)
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cpumask_set_cpu(cpu, mask);
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}
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/* check MCG_CTL on all the cpus on this node */
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static int amd64_mcg_ctl_enabled_on_cpus(const cpumask_t *mask)
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static bool amd64_nb_mce_bank_enabled_on_node(int nid)
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{
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int ret = 1;
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preempt_disable();
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smp_call_function_many(mask, check_mcg_ctl, &ret, 1);
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preempt_enable();
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cpumask_t mask;
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struct msr *msrs;
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int cpu, nbe, idx = 0;
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bool ret = false;
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cpumask_clear(&mask);
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get_cpus_on_this_dct_cpumask(&mask, nid);
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msrs = kzalloc(sizeof(struct msr) * cpumask_weight(&mask), GFP_KERNEL);
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if (!msrs) {
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amd64_printk(KERN_WARNING, "%s: error allocating msrs\n",
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__func__);
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return false;
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}
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rdmsr_on_cpus(&mask, MSR_IA32_MCG_CTL, msrs);
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for_each_cpu(cpu, &mask) {
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nbe = msrs[idx].l & K8_MSR_MCGCTL_NBE;
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debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
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cpu, msrs[idx].q,
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(nbe ? "enabled" : "disabled"));
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if (!nbe)
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goto out;
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idx++;
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}
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ret = true;
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out:
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kfree(msrs);
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return ret;
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}
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@ -2799,71 +2797,46 @@ static int amd64_mcg_ctl_enabled_on_cpus(const cpumask_t *mask)
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* the memory system completely. A command line option allows to force-enable
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* hardware ECC later in amd64_enable_ecc_error_reporting().
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*/
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static const char *ecc_warning =
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"WARNING: ECC is disabled by BIOS. Module will NOT be loaded.\n"
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" Either Enable ECC in the BIOS, or set 'ecc_enable_override'.\n"
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" Also, use of the override can cause unknown side effects.\n";
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static int amd64_check_ecc_enabled(struct amd64_pvt *pvt)
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{
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u32 value;
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int err = 0, ret = 0;
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int err = 0;
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u8 ecc_enabled = 0;
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bool nb_mce_en = false;
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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debugf0("Reading K8_NBCTL failed\n");
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ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE);
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if (!ecc_enabled)
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amd64_printk(KERN_WARNING, "This node reports that Memory ECC "
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"is currently disabled, set F3x%x[22] (%s).\n",
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K8_NBCFG, pci_name(pvt->misc_f3_ctl));
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else
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amd64_printk(KERN_INFO, "ECC is enabled by BIOS.\n");
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ret = amd64_mcg_ctl_enabled_on_cpus(cpumask_of_node(pvt->mc_node_id));
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nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id);
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if (!nb_mce_en)
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amd64_printk(KERN_WARNING, "NB MCE bank disabled, set MSR "
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"0x%08x[4] on node %d to enable.\n",
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MSR_IA32_MCG_CTL, pvt->mc_node_id);
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debugf0("K8_NBCFG=0x%x, DRAM ECC is %s\n", value,
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(value & K8_NBCFG_ECC_ENABLE ? "enabled" : "disabled"));
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if (!ecc_enabled || !ret) {
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if (!ecc_enabled) {
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amd64_printk(KERN_WARNING, "This node reports that "
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"Memory ECC is currently "
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"disabled.\n");
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amd64_printk(KERN_WARNING, "bit 0x%lx in register "
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"F3x%x of the MISC_CONTROL device (%s) "
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"should be enabled\n", K8_NBCFG_ECC_ENABLE,
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K8_NBCFG, pci_name(pvt->misc_f3_ctl));
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}
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if (!ret) {
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amd64_printk(KERN_WARNING, "bit 0x%016lx in MSR 0x%08x "
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"of node %d should be enabled\n",
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K8_MSR_MCGCTL_NBE, MSR_IA32_MCG_CTL,
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pvt->mc_node_id);
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}
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if (!ecc_enabled || !nb_mce_en) {
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if (!ecc_enable_override) {
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amd64_printk(KERN_WARNING, "WARNING: ECC is NOT "
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"currently enabled by the BIOS. Module "
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"will NOT be loaded.\n"
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" Either Enable ECC in the BIOS, "
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"or use the 'ecc_enable_override' "
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"parameter.\n"
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" Might be a BIOS bug, if BIOS says "
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"ECC is enabled\n"
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" Use of the override can cause "
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"unknown side effects.\n");
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ret = -ENODEV;
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} else
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/*
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* enable further driver loading if ECC enable is
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* overridden.
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*/
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ret = 0;
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} else {
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amd64_printk(KERN_INFO,
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"ECC is enabled by BIOS, Proceeding "
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"with EDAC module initialization\n");
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/* Signal good ECC status */
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ret = 0;
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amd64_printk(KERN_WARNING, "%s", ecc_warning);
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return -ENODEV;
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}
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} else
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/* CLEAR the override, since BIOS controlled it */
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ecc_enable_override = 0;
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}
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return ret;
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return 0;
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}
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struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) +
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@ -405,7 +405,7 @@ void decode_mce(struct mce *m)
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regs.nbsh = (u32)(m->status >> 32);
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regs.nbeal = (u32) m->addr;
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regs.nbeah = (u32)(m->addr >> 32);
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node = per_cpu(cpu_llc_id, m->extcpu);
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node = amd_get_nb_id(m->extcpu);
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amd_decode_nb_mce(node, ®s, 1);
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break;
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