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ARC: fold __builtin_constant_p() into test_bit()
This makes test_bit() more like its siblings *_bit() routines. Also add some comments about the constant @nr micro-optimization Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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1 changed files with 18 additions and 13 deletions
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@ -32,6 +32,20 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *m)
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m += nr >> 5;
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/*
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* ARC ISA micro-optimization:
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*
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* Instructions dealing with bitpos only consider lower 5 bits (0-31)
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* e.g (x << 33) is handled like (x << 1) by ASL instruction
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* (mem pointer still needs adjustment to point to next word)
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*
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* Hence the masking to clamp @nr arg can be elided in general.
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*
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* However if @nr is a constant (above assumed it in a register),
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* and greater than 31, gcc can optimize away (x << 33) to 0,
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* as overflow, given the 32-bit ISA. Thus masking needs to be done
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* for constant @nr, but no code is generated due to const prop.
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*/
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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@ -374,29 +388,20 @@ __test_and_change_bit(unsigned long nr, volatile unsigned long *m)
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* This routine doesn't need to be atomic.
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*/
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static inline int
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__constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
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{
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return ((1UL << (nr & 31)) &
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(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
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}
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static inline int
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__test_bit(unsigned int nr, const volatile unsigned long *addr)
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test_bit(unsigned int nr, const volatile unsigned long *addr)
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{
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unsigned long mask;
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addr += nr >> 5;
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/* ARC700 only considers 5 bits in bit-fiddling insn */
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if (__builtin_constant_p(nr))
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nr &= 0x1f;
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mask = 1 << nr;
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return ((mask & *addr) != 0);
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}
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#define test_bit(nr, addr) (__builtin_constant_p(nr) ? \
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__constant_test_bit((nr), (addr)) : \
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__test_bit((nr), (addr)))
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/*
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* Count the number of zeros, starting from MSB
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* Helper for fls( ) friends
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