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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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[SCSI] qla4xxx: Rename 82XX macros
Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com> Reviewed-by: Mike Christie <michaelc@cs.wisc.edu> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
parent
5e9bcec792
commit
de8c72daa0
7 changed files with 139 additions and 139 deletions
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@ -77,13 +77,13 @@ qla4_8xxx_sysfs_write_fw_dump(struct file *filep, struct kobject *kobj,
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/* Reset HBA */
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qla4_82xx_idc_lock(ha);
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dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
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if (dev_state == QLA82XX_DEV_READY) {
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if (dev_state == QLA8XXX_DEV_READY) {
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ql4_printk(KERN_INFO, ha,
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"%s: Setting Need reset, reset_owner is 0x%x.\n",
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__func__, ha->func_num);
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qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
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QLA82XX_DEV_NEED_RESET);
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set_bit(AF_82XX_RST_OWNER, &ha->flags);
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QLA8XXX_DEV_NEED_RESET);
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set_bit(AF_8XXX_RST_OWNER, &ha->flags);
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} else
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ql4_printk(KERN_INFO, ha,
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"%s: Reset not performed as device state is 0x%x\n",
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@ -497,7 +497,7 @@ struct scsi_qla_host {
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#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
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#define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
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#define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
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#define AF_82XX_RST_OWNER 25 /* 0x02000000 */
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#define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
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#define AF_82XX_DUMP_READING 26 /* 0x04000000 */
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unsigned long dpc_flags;
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@ -1195,9 +1195,9 @@ struct ql_iscsi_stats {
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uint8_t reserved2[264]; /* 0x0308 - 0x040F */
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};
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#define QLA82XX_DBG_STATE_ARRAY_LEN 16
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#define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8
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#define QLA82XX_DBG_RSVD_ARRAY_LEN 8
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#define QLA8XXX_DBG_STATE_ARRAY_LEN 16
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#define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN 8
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#define QLA8XXX_DBG_RSVD_ARRAY_LEN 8
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struct qla4_8xxx_minidump_template_hdr {
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uint32_t entry_type;
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@ -1214,8 +1214,8 @@ struct qla4_8xxx_minidump_template_hdr {
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uint32_t driver_info_word3;
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uint32_t driver_info_word4;
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uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN];
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uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN];
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uint32_t saved_state_array[QLA8XXX_DBG_STATE_ARRAY_LEN];
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uint32_t capture_size_array[QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN];
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};
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#endif /* _QLA4X_FW_H */
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@ -88,7 +88,7 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
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qla4_82xx_idc_lock(ha);
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dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
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qla4_82xx_idc_unlock(ha);
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if (dev_state == QLA82XX_DEV_FAILED) {
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if (dev_state == QLA8XXX_DEV_FAILED) {
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ql4_printk(KERN_WARNING, ha,
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"scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
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ha->host_no, __func__);
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@ -563,7 +563,7 @@ qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
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}
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/* PCI Windowing for DDR regions. */
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#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
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#define QLA8XXX_ADDR_IN_RANGE(addr, low, high) \
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(((addr) <= (high)) && ((addr) >= (low)))
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/*
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@ -574,10 +574,10 @@ static unsigned long
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qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
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unsigned long long addr, int size)
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{
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if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
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QLA82XX_ADDR_DDR_NET_MAX) ||
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!QLA82XX_ADDR_IN_RANGE(addr + size - 1,
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QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
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if (!QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
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QLA8XXX_ADDR_DDR_NET_MAX) ||
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!QLA8XXX_ADDR_IN_RANGE(addr + size - 1,
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QLA8XXX_ADDR_DDR_NET, QLA8XXX_ADDR_DDR_NET_MAX) ||
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((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
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return 0;
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}
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@ -592,8 +592,8 @@ qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
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int window;
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u32 win_read;
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if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
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QLA82XX_ADDR_DDR_NET_MAX)) {
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if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
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QLA8XXX_ADDR_DDR_NET_MAX)) {
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/* DDR network side */
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window = MN_WIN(addr);
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ha->ddr_mn_window = window;
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@ -607,8 +607,8 @@ qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
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__func__, window, win_read);
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}
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addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
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} else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
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QLA82XX_ADDR_OCM0_MAX)) {
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} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
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QLA8XXX_ADDR_OCM0_MAX)) {
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unsigned int temp1;
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/* if bits 19:18&17:11 are on */
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if ((addr & 0x00ff800) == 0xff800) {
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@ -630,7 +630,7 @@ qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
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}
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addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
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} else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
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} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
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QLA82XX_P3_ADDR_QDR_NET_MAX)) {
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/* QDR network side */
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window = MS_WIN(addr);
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@ -669,20 +669,20 @@ static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
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qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
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if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
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QLA82XX_ADDR_DDR_NET_MAX)) {
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if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
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QLA8XXX_ADDR_DDR_NET_MAX)) {
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/* DDR network side */
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BUG(); /* MN access can not come here */
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} else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
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QLA82XX_ADDR_OCM0_MAX)) {
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} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
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QLA8XXX_ADDR_OCM0_MAX)) {
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return 1;
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} else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
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QLA82XX_ADDR_OCM1_MAX)) {
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} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
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QLA8XXX_ADDR_OCM1_MAX)) {
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return 1;
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} else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
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} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
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qdr_max)) {
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/* QDR network side */
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window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
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window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
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if (ha->qdr_sn_window == window)
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return 1;
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}
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@ -1250,7 +1250,7 @@ qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
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* If not MN, go check for MS or invalid.
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*/
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if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
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if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
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mem_crb = QLA82XX_CRB_QDR_NET;
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else {
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mem_crb = QLA82XX_CRB_DDR_NET;
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@ -1340,7 +1340,7 @@ qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
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/*
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* If not MN, go check for MS or invalid.
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*/
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if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
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if (off >= QLA8XXX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
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mem_crb = QLA82XX_CRB_QDR_NET;
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else {
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mem_crb = QLA82XX_CRB_DDR_NET;
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@ -1744,33 +1744,33 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
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crb_addr = crb_entry->addr;
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for (i = 0; i < crb_entry->op_count; i++) {
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opcode = crb_entry->crb_ctrl.opcode;
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if (opcode & QLA82XX_DBG_OPCODE_WR) {
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if (opcode & QLA8XXX_DBG_OPCODE_WR) {
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qla4_8xxx_md_rw_32(ha, crb_addr,
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crb_entry->value_1, 1);
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opcode &= ~QLA82XX_DBG_OPCODE_WR;
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opcode &= ~QLA8XXX_DBG_OPCODE_WR;
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}
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if (opcode & QLA82XX_DBG_OPCODE_RW) {
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if (opcode & QLA8XXX_DBG_OPCODE_RW) {
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read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
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qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
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opcode &= ~QLA82XX_DBG_OPCODE_RW;
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opcode &= ~QLA8XXX_DBG_OPCODE_RW;
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}
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if (opcode & QLA82XX_DBG_OPCODE_AND) {
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if (opcode & QLA8XXX_DBG_OPCODE_AND) {
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read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
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read_value &= crb_entry->value_2;
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opcode &= ~QLA82XX_DBG_OPCODE_AND;
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if (opcode & QLA82XX_DBG_OPCODE_OR) {
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opcode &= ~QLA8XXX_DBG_OPCODE_AND;
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if (opcode & QLA8XXX_DBG_OPCODE_OR) {
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read_value |= crb_entry->value_3;
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opcode &= ~QLA82XX_DBG_OPCODE_OR;
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opcode &= ~QLA8XXX_DBG_OPCODE_OR;
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}
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qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
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}
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if (opcode & QLA82XX_DBG_OPCODE_OR) {
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if (opcode & QLA8XXX_DBG_OPCODE_OR) {
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read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
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read_value |= crb_entry->value_3;
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qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
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opcode &= ~QLA82XX_DBG_OPCODE_OR;
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opcode &= ~QLA8XXX_DBG_OPCODE_OR;
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}
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if (opcode & QLA82XX_DBG_OPCODE_POLL) {
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if (opcode & QLA8XXX_DBG_OPCODE_POLL) {
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poll_time = crb_entry->crb_strd.poll_timeout;
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wtime = jiffies + poll_time;
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read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
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@ -1787,10 +1787,10 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
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read_value = qla4_8xxx_md_rw_32(ha,
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crb_addr, 0, 0);
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} while (1);
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opcode &= ~QLA82XX_DBG_OPCODE_POLL;
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opcode &= ~QLA8XXX_DBG_OPCODE_POLL;
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}
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if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
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if (opcode & QLA8XXX_DBG_OPCODE_RDSTATE) {
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if (crb_entry->crb_strd.state_index_a) {
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index = crb_entry->crb_strd.state_index_a;
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addr = tmplt_hdr->saved_state_array[index];
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@ -1801,10 +1801,10 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
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read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0);
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index = crb_entry->crb_ctrl.state_index_v;
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tmplt_hdr->saved_state_array[index] = read_value;
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opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
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opcode &= ~QLA8XXX_DBG_OPCODE_RDSTATE;
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}
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if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
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if (opcode & QLA8XXX_DBG_OPCODE_WRSTATE) {
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if (crb_entry->crb_strd.state_index_a) {
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index = crb_entry->crb_strd.state_index_a;
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addr = tmplt_hdr->saved_state_array[index];
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@ -1821,10 +1821,10 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
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}
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qla4_8xxx_md_rw_32(ha, addr, read_value, 1);
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opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
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opcode &= ~QLA8XXX_DBG_OPCODE_WRSTATE;
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}
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if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
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if (opcode & QLA8XXX_DBG_OPCODE_MDSTATE) {
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index = crb_entry->crb_ctrl.state_index_v;
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read_value = tmplt_hdr->saved_state_array[index];
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read_value <<= crb_entry->crb_ctrl.shl;
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@ -1834,7 +1834,7 @@ static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
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read_value |= crb_entry->value_3;
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read_value += crb_entry->value_1;
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tmplt_hdr->saved_state_array[index] = read_value;
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opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
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opcode &= ~QLA8XXX_DBG_OPCODE_MDSTATE;
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}
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crb_addr += crb_entry->crb_strd.addr_stride;
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}
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@ -2081,7 +2081,7 @@ static void qla4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
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struct qla8xxx_minidump_entry_hdr *entry_hdr,
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int index)
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{
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entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
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entry_hdr->d_ctrl.driver_flags |= QLA8XXX_DBG_SKIPPED_FLAG;
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DEBUG2(ql4_printk(KERN_INFO, ha,
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"scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
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ha->host_no, index, entry_hdr->entry_type,
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@ -2147,7 +2147,7 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
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if (!(entry_hdr->d_ctrl.entry_capture_mask &
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ha->fw_dump_capture_mask)) {
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entry_hdr->d_ctrl.driver_flags |=
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QLA82XX_DBG_SKIPPED_FLAG;
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QLA8XXX_DBG_SKIPPED_FLAG;
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goto skip_nxt_entry;
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}
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@ -2160,10 +2160,10 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
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* debug data
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*/
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switch (entry_hdr->entry_type) {
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case QLA82XX_RDEND:
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case QLA8XXX_RDEND:
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qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
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break;
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case QLA82XX_CNTRL:
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case QLA8XXX_CNTRL:
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rval = qla4_8xxx_minidump_process_control(ha,
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entry_hdr);
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if (rval != QLA_SUCCESS) {
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@ -2171,11 +2171,11 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
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goto md_failed;
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}
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break;
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case QLA82XX_RDCRB:
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case QLA8XXX_RDCRB:
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qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
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&data_ptr);
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break;
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case QLA82XX_RDMEM:
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case QLA8XXX_RDMEM:
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rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
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&data_ptr);
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if (rval != QLA_SUCCESS) {
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@ -2183,15 +2183,15 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
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goto md_failed;
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}
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break;
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case QLA82XX_BOARD:
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case QLA82XX_RDROM:
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case QLA8XXX_BOARD:
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case QLA8XXX_RDROM:
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qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
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&data_ptr);
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break;
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case QLA82XX_L2DTG:
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case QLA82XX_L2ITG:
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case QLA82XX_L2DAT:
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case QLA82XX_L2INS:
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case QLA8XXX_L2DTG:
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case QLA8XXX_L2ITG:
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case QLA8XXX_L2DAT:
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case QLA8XXX_L2INS:
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rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
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&data_ptr);
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if (rval != QLA_SUCCESS) {
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@ -2199,24 +2199,24 @@ static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
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goto md_failed;
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}
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break;
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case QLA82XX_L1DAT:
|
||||
case QLA82XX_L1INS:
|
||||
case QLA8XXX_L1DAT:
|
||||
case QLA8XXX_L1INS:
|
||||
qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
|
||||
&data_ptr);
|
||||
break;
|
||||
case QLA82XX_RDOCM:
|
||||
case QLA8XXX_RDOCM:
|
||||
qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
|
||||
&data_ptr);
|
||||
break;
|
||||
case QLA82XX_RDMUX:
|
||||
case QLA8XXX_RDMUX:
|
||||
qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
|
||||
&data_ptr);
|
||||
break;
|
||||
case QLA82XX_QUEUE:
|
||||
case QLA8XXX_QUEUE:
|
||||
qla4_8xxx_minidump_process_queue(ha, entry_hdr,
|
||||
&data_ptr);
|
||||
break;
|
||||
case QLA82XX_RDNOP:
|
||||
case QLA8XXX_RDNOP:
|
||||
default:
|
||||
qla4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
|
||||
break;
|
||||
|
@ -2289,7 +2289,7 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
|
|||
timeout = msleep_interruptible(200);
|
||||
if (timeout) {
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
||||
QLA82XX_DEV_FAILED);
|
||||
QLA8XXX_DEV_FAILED);
|
||||
return rval;
|
||||
}
|
||||
|
||||
|
@ -2319,7 +2319,7 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
|
|||
dev_initialize:
|
||||
/* set to DEV_INITIALIZING */
|
||||
ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
|
||||
|
||||
/* Driver that sets device state to initializating sets IDC version */
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
|
||||
|
@ -2340,13 +2340,13 @@ qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
|
|||
if (rval != QLA_SUCCESS) {
|
||||
ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
|
||||
qla4_8xxx_clear_drv_active(ha);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
|
||||
return rval;
|
||||
}
|
||||
|
||||
dev_ready:
|
||||
ql4_printk(KERN_INFO, ha, "HW State: READY\n");
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
|
||||
|
||||
return rval;
|
||||
}
|
||||
|
@ -2373,7 +2373,7 @@ qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
|
|||
qla4_82xx_idc_lock(ha);
|
||||
}
|
||||
|
||||
if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
|
||||
if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
|
||||
DEBUG2(ql4_printk(KERN_INFO, ha,
|
||||
"%s(%ld): reset acknowledged\n",
|
||||
__func__, ha->host_no));
|
||||
|
@ -2404,7 +2404,7 @@ qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
|
|||
* When reset_owner times out, check which functions
|
||||
* acked/did not ack
|
||||
*/
|
||||
if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
|
||||
if (test_bit(AF_8XXX_RST_OWNER, &ha->flags)) {
|
||||
ql4_printk(KERN_INFO, ha,
|
||||
"%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
|
||||
__func__, ha->host_no, drv_state,
|
||||
|
@ -2419,16 +2419,16 @@ qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
|
|||
}
|
||||
|
||||
/* Clear RESET OWNER as we are not going to use it any further */
|
||||
clear_bit(AF_82XX_RST_OWNER, &ha->flags);
|
||||
clear_bit(AF_8XXX_RST_OWNER, &ha->flags);
|
||||
|
||||
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
|
||||
ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
|
||||
dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
|
||||
|
||||
/* Force to DEV_COLD unless someone else is starting a reset */
|
||||
if (dev_state != QLA82XX_DEV_INITIALIZING) {
|
||||
if (dev_state != QLA8XXX_DEV_INITIALIZING) {
|
||||
ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
|
||||
qla4_8xxx_set_rst_ready(ha);
|
||||
}
|
||||
}
|
||||
|
@ -2481,7 +2481,7 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
|
|||
dev_state, dev_state < MAX_STATES ?
|
||||
qdev_state[dev_state] : "Unknown");
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
||||
QLA82XX_DEV_FAILED);
|
||||
QLA8XXX_DEV_FAILED);
|
||||
}
|
||||
|
||||
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
|
||||
|
@ -2491,17 +2491,17 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
|
|||
|
||||
/* NOTE: Make sure idc unlocked upon exit of switch statement */
|
||||
switch (dev_state) {
|
||||
case QLA82XX_DEV_READY:
|
||||
case QLA8XXX_DEV_READY:
|
||||
goto exit;
|
||||
case QLA82XX_DEV_COLD:
|
||||
case QLA8XXX_DEV_COLD:
|
||||
rval = qla4_8xxx_device_bootstrap(ha);
|
||||
goto exit;
|
||||
case QLA82XX_DEV_INITIALIZING:
|
||||
case QLA8XXX_DEV_INITIALIZING:
|
||||
qla4_82xx_idc_unlock(ha);
|
||||
msleep(1000);
|
||||
qla4_82xx_idc_lock(ha);
|
||||
break;
|
||||
case QLA82XX_DEV_NEED_RESET:
|
||||
case QLA8XXX_DEV_NEED_RESET:
|
||||
if (!ql4xdontresethba) {
|
||||
qla4_82xx_need_reset_handler(ha);
|
||||
/* Update timeout value after need
|
||||
|
@ -2514,16 +2514,16 @@ int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
|
|||
qla4_82xx_idc_lock(ha);
|
||||
}
|
||||
break;
|
||||
case QLA82XX_DEV_NEED_QUIESCENT:
|
||||
case QLA8XXX_DEV_NEED_QUIESCENT:
|
||||
/* idc locked/unlocked in handler */
|
||||
qla4_8xxx_need_qsnt_handler(ha);
|
||||
break;
|
||||
case QLA82XX_DEV_QUIESCENT:
|
||||
case QLA8XXX_DEV_QUIESCENT:
|
||||
qla4_82xx_idc_unlock(ha);
|
||||
msleep(1000);
|
||||
qla4_82xx_idc_lock(ha);
|
||||
break;
|
||||
case QLA82XX_DEV_FAILED:
|
||||
case QLA8XXX_DEV_FAILED:
|
||||
qla4_82xx_idc_unlock(ha);
|
||||
qla4xxx_dead_adapter_cleanup(ha);
|
||||
rval = QLA_ERROR;
|
||||
|
@ -2884,11 +2884,11 @@ qla4_82xx_isp_reset(struct scsi_qla_host *ha)
|
|||
qla4_82xx_idc_lock(ha);
|
||||
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
|
||||
|
||||
if (dev_state == QLA82XX_DEV_READY) {
|
||||
if (dev_state == QLA8XXX_DEV_READY) {
|
||||
ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
||||
QLA82XX_DEV_NEED_RESET);
|
||||
set_bit(AF_82XX_RST_OWNER, &ha->flags);
|
||||
QLA8XXX_DEV_NEED_RESET);
|
||||
set_bit(AF_8XXX_RST_OWNER, &ha->flags);
|
||||
} else
|
||||
ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
|
||||
|
||||
|
|
|
@ -490,8 +490,8 @@ enum {
|
|||
* Base addresses of major components on-chip.
|
||||
* ====================== BASE ADDRESSES ON-CHIP ======================
|
||||
*/
|
||||
#define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
|
||||
#define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
|
||||
#define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)
|
||||
#define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
|
||||
|
||||
/* Imbus address bit used to indicate a host address. This bit is
|
||||
* eliminated by the pcie bar and bar select before presentation
|
||||
|
@ -500,11 +500,11 @@ enum {
|
|||
#define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
|
||||
#define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
|
||||
#define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
|
||||
#define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
|
||||
#define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
|
||||
#define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
|
||||
#define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
|
||||
#define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
|
||||
#define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)
|
||||
#define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)
|
||||
#define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)
|
||||
#define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)
|
||||
#define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)
|
||||
|
||||
#define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
|
||||
#define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
|
||||
|
@ -572,13 +572,13 @@ enum {
|
|||
#define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
|
||||
|
||||
/* Every driver should use these Device State */
|
||||
#define QLA82XX_DEV_COLD 1
|
||||
#define QLA82XX_DEV_INITIALIZING 2
|
||||
#define QLA82XX_DEV_READY 3
|
||||
#define QLA82XX_DEV_NEED_RESET 4
|
||||
#define QLA82XX_DEV_NEED_QUIESCENT 5
|
||||
#define QLA82XX_DEV_FAILED 6
|
||||
#define QLA82XX_DEV_QUIESCENT 7
|
||||
#define QLA8XXX_DEV_COLD 1
|
||||
#define QLA8XXX_DEV_INITIALIZING 2
|
||||
#define QLA8XXX_DEV_READY 3
|
||||
#define QLA8XXX_DEV_NEED_RESET 4
|
||||
#define QLA8XXX_DEV_NEED_QUIESCENT 5
|
||||
#define QLA8XXX_DEV_FAILED 6
|
||||
#define QLA8XXX_DEV_QUIESCENT 7
|
||||
#define MAX_STATES 8 /* Increment if new state added */
|
||||
|
||||
#define QLA82XX_IDC_VERSION 0x1
|
||||
|
@ -795,41 +795,41 @@ struct crb_addr_pair {
|
|||
/* Minidump related */
|
||||
|
||||
/* Entry Type Defines */
|
||||
#define QLA82XX_RDNOP 0
|
||||
#define QLA82XX_RDCRB 1
|
||||
#define QLA82XX_RDMUX 2
|
||||
#define QLA82XX_QUEUE 3
|
||||
#define QLA82XX_BOARD 4
|
||||
#define QLA82XX_RDOCM 6
|
||||
#define QLA82XX_PREGS 7
|
||||
#define QLA82XX_L1DTG 8
|
||||
#define QLA82XX_L1ITG 9
|
||||
#define QLA82XX_L1DAT 11
|
||||
#define QLA82XX_L1INS 12
|
||||
#define QLA82XX_L2DTG 21
|
||||
#define QLA82XX_L2ITG 22
|
||||
#define QLA82XX_L2DAT 23
|
||||
#define QLA82XX_L2INS 24
|
||||
#define QLA82XX_RDROM 71
|
||||
#define QLA82XX_RDMEM 72
|
||||
#define QLA82XX_CNTRL 98
|
||||
#define QLA82XX_RDEND 255
|
||||
#define QLA8XXX_RDNOP 0
|
||||
#define QLA8XXX_RDCRB 1
|
||||
#define QLA8XXX_RDMUX 2
|
||||
#define QLA8XXX_QUEUE 3
|
||||
#define QLA8XXX_BOARD 4
|
||||
#define QLA8XXX_RDOCM 6
|
||||
#define QLA8XXX_PREGS 7
|
||||
#define QLA8XXX_L1DTG 8
|
||||
#define QLA8XXX_L1ITG 9
|
||||
#define QLA8XXX_L1DAT 11
|
||||
#define QLA8XXX_L1INS 12
|
||||
#define QLA8XXX_L2DTG 21
|
||||
#define QLA8XXX_L2ITG 22
|
||||
#define QLA8XXX_L2DAT 23
|
||||
#define QLA8XXX_L2INS 24
|
||||
#define QLA8XXX_RDROM 71
|
||||
#define QLA8XXX_RDMEM 72
|
||||
#define QLA8XXX_CNTRL 98
|
||||
#define QLA8XXX_RDEND 255
|
||||
|
||||
/* Opcodes for Control Entries.
|
||||
* These Flags are bit fields.
|
||||
*/
|
||||
#define QLA82XX_DBG_OPCODE_WR 0x01
|
||||
#define QLA82XX_DBG_OPCODE_RW 0x02
|
||||
#define QLA82XX_DBG_OPCODE_AND 0x04
|
||||
#define QLA82XX_DBG_OPCODE_OR 0x08
|
||||
#define QLA82XX_DBG_OPCODE_POLL 0x10
|
||||
#define QLA82XX_DBG_OPCODE_RDSTATE 0x20
|
||||
#define QLA82XX_DBG_OPCODE_WRSTATE 0x40
|
||||
#define QLA82XX_DBG_OPCODE_MDSTATE 0x80
|
||||
#define QLA8XXX_DBG_OPCODE_WR 0x01
|
||||
#define QLA8XXX_DBG_OPCODE_RW 0x02
|
||||
#define QLA8XXX_DBG_OPCODE_AND 0x04
|
||||
#define QLA8XXX_DBG_OPCODE_OR 0x08
|
||||
#define QLA8XXX_DBG_OPCODE_POLL 0x10
|
||||
#define QLA8XXX_DBG_OPCODE_RDSTATE 0x20
|
||||
#define QLA8XXX_DBG_OPCODE_WRSTATE 0x40
|
||||
#define QLA8XXX_DBG_OPCODE_MDSTATE 0x80
|
||||
|
||||
/* Driver Flags */
|
||||
#define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
|
||||
#define QLA82XX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size
|
||||
#define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
|
||||
#define QLA8XXX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size
|
||||
* mismatch */
|
||||
|
||||
/* Driver_code is for driver to write some info about the entry
|
||||
|
|
|
@ -2525,7 +2525,7 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
|
|||
CRB_NIU_XG_PAUSE_CTL_P1);
|
||||
set_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
|
||||
qla4xxx_wake_dpc(ha);
|
||||
} else if (dev_state == QLA82XX_DEV_NEED_RESET &&
|
||||
} else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
|
||||
!test_bit(DPC_RESET_HA, &ha->dpc_flags)) {
|
||||
if (!ql4xdontresethba) {
|
||||
ql4_printk(KERN_INFO, ha, "%s: HW State: "
|
||||
|
@ -2533,7 +2533,7 @@ void qla4_8xxx_watchdog(struct scsi_qla_host *ha)
|
|||
set_bit(DPC_RESET_HA, &ha->dpc_flags);
|
||||
qla4xxx_wake_dpc(ha);
|
||||
}
|
||||
} else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT &&
|
||||
} else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
|
||||
!test_bit(DPC_HA_NEED_QUIESCENT, &ha->dpc_flags)) {
|
||||
ql4_printk(KERN_INFO, ha, "%s: HW State: NEED QUIES!\n",
|
||||
__func__);
|
||||
|
@ -3043,7 +3043,7 @@ static int qla4xxx_recover_adapter(struct scsi_qla_host *ha)
|
|||
qla4_82xx_idc_lock(ha);
|
||||
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
|
||||
qla4_82xx_idc_unlock(ha);
|
||||
if (dev_state == QLA82XX_DEV_FAILED) {
|
||||
if (dev_state == QLA8XXX_DEV_FAILED) {
|
||||
ql4_printk(KERN_INFO, ha, "%s: don't retry "
|
||||
"recover adapter. H/W is in Failed "
|
||||
"state\n", __func__);
|
||||
|
@ -3387,7 +3387,7 @@ static void qla4xxx_do_dpc(struct work_struct *work)
|
|||
if (test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags)) {
|
||||
qla4_82xx_idc_lock(ha);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
||||
QLA82XX_DEV_FAILED);
|
||||
QLA8XXX_DEV_FAILED);
|
||||
qla4_82xx_idc_unlock(ha);
|
||||
ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
|
||||
qla4_8xxx_device_state_handler(ha);
|
||||
|
@ -5164,7 +5164,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
|
|||
qla4_82xx_idc_lock(ha);
|
||||
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
|
||||
qla4_82xx_idc_unlock(ha);
|
||||
if (dev_state == QLA82XX_DEV_FAILED) {
|
||||
if (dev_state == QLA8XXX_DEV_FAILED) {
|
||||
ql4_printk(KERN_WARNING, ha, "%s: don't retry "
|
||||
"initialize adapter. H/W is in failed state\n",
|
||||
__func__);
|
||||
|
@ -5188,7 +5188,7 @@ static int __devinit qla4xxx_probe_adapter(struct pci_dev *pdev,
|
|||
DEBUG2(printk(KERN_ERR "HW STATE: FAILED\n"));
|
||||
qla4_82xx_idc_lock(ha);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
||||
QLA82XX_DEV_FAILED);
|
||||
QLA8XXX_DEV_FAILED);
|
||||
qla4_82xx_idc_unlock(ha);
|
||||
}
|
||||
ret = -ENODEV;
|
||||
|
@ -6035,7 +6035,7 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
|
|||
|
||||
qla4_82xx_idc_lock(ha);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
||||
QLA82XX_DEV_COLD);
|
||||
QLA8XXX_DEV_COLD);
|
||||
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
|
||||
QLA82XX_IDC_VERSION);
|
||||
|
@ -6050,12 +6050,12 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
|
|||
"FAILED\n", ha->host_no, __func__);
|
||||
qla4_8xxx_clear_drv_active(ha);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
||||
QLA82XX_DEV_FAILED);
|
||||
QLA8XXX_DEV_FAILED);
|
||||
} else {
|
||||
ql4_printk(KERN_INFO, ha, "scsi%ld: %s: HW State: "
|
||||
"READY\n", ha->host_no, __func__);
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
|
||||
QLA82XX_DEV_READY);
|
||||
QLA8XXX_DEV_READY);
|
||||
/* Clear driver state register */
|
||||
qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
|
||||
qla4_8xxx_set_drv_active(ha);
|
||||
|
@ -6076,7 +6076,7 @@ static uint32_t qla4_8xxx_error_recovery(struct scsi_qla_host *ha)
|
|||
"the reset owner\n", ha->host_no, __func__,
|
||||
ha->pdev->devfn);
|
||||
if ((qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
|
||||
QLA82XX_DEV_READY)) {
|
||||
QLA8XXX_DEV_READY)) {
|
||||
clear_bit(AF_FW_RECOVERY, &ha->flags);
|
||||
rval = qla4xxx_initialize_adapter(ha, RESET_ADAPTER);
|
||||
if (rval == QLA_SUCCESS) {
|
||||
|
|
Loading…
Reference in a new issue