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drm/amdgpu: cleanup the write_pte implementations
We don't need the gart mapping handling here any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b7fc2cbd5e
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de9ea7bd36
5 changed files with 53 additions and 97 deletions
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@ -250,10 +250,9 @@ struct amdgpu_vm_pte_funcs {
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uint64_t pe, uint64_t src,
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unsigned count);
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/* write pte one entry at a time with addr mapping */
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void (*write_pte)(struct amdgpu_ib *ib,
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const dma_addr_t *pages_addr, uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags);
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void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
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uint64_t value, unsigned count,
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uint32_t incr);
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/* for linear pte/pde updates without addr mapping */
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void (*set_pte_pde)(struct amdgpu_ib *ib,
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uint64_t pe,
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@ -965,7 +964,6 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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struct amdgpu_job *job);
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int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
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void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
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uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
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int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
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@ -2271,7 +2269,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
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#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
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#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
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#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
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#define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
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#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
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#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
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#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
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#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
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@ -491,8 +491,8 @@ static void amdgpu_vm_update_pages(struct amdgpu_pte_update_params *params,
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pe, (params->src + (addr >> 12) * 8), count);
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} else if (count < 3) {
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amdgpu_vm_write_pte(params->adev, params->ib, NULL, pe, addr,
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count, incr, flags);
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amdgpu_vm_write_pte(params->adev, params->ib, pe,
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addr | flags, count, incr);
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} else {
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amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
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@ -569,21 +569,15 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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* Look up the physical address of the page that the pte resolves
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* to and return the pointer for the page table entry.
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*/
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uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
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static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
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{
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uint64_t result;
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if (pages_addr) {
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/* page table offset */
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result = pages_addr[addr >> PAGE_SHIFT];
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/* page table offset */
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result = pages_addr[addr >> PAGE_SHIFT];
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/* in case cpu page size != gpu page size*/
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result |= addr & (~PAGE_MASK);
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} else {
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/* No mapping required */
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result = addr;
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}
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/* in case cpu page size != gpu page size*/
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result |= addr & (~PAGE_MASK);
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result &= 0xFFFFFFFFFFFFF000ULL;
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@ -719,39 +719,27 @@ static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
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*
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @value: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: access flags
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*
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* Update PTEs by writing them manually using sDMA (CIK).
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*/
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static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
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const dma_addr_t *pages_addr, uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
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uint64_t value, unsigned count,
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uint32_t incr)
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{
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uint64_t value;
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unsigned ndw;
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unsigned ndw = count * 2;
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
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SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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value = amdgpu_vm_map_gart(pages_addr, addr);
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addr += incr;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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}
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ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
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SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
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ib->ptr[ib->length_dw++] = lower_32_bits(pe);
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2) {
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ib->ptr[ib->length_dw++] = lower_32_bits(value);
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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value += incr;
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}
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}
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@ -774,39 +774,27 @@ static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
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*
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @value: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: access flags
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*
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* Update PTEs by writing them manually using sDMA (CIK).
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*/
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static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
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const dma_addr_t *pages_addr, uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
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uint64_t value, unsigned count,
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uint32_t incr)
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{
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uint64_t value;
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unsigned ndw;
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unsigned ndw = count * 2;
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
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SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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value = amdgpu_vm_map_gart(pages_addr, addr);
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addr += incr;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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}
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ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
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SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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ib->ptr[ib->length_dw++] = lower_32_bits(value);
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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value += incr;
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}
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}
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@ -1001,39 +1001,27 @@ static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
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*
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* @ib: indirect buffer to fill with commands
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @value: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: access flags
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*
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* Update PTEs by writing them manually using sDMA (CIK).
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*/
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static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib,
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const dma_addr_t *pages_addr, uint64_t pe,
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uint64_t addr, unsigned count,
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uint32_t incr, uint32_t flags)
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static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
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uint64_t value, unsigned count,
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uint32_t incr)
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{
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uint64_t value;
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unsigned ndw;
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unsigned ndw = count * 2;
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
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SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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value = amdgpu_vm_map_gart(pages_addr, addr);
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addr += incr;
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value |= flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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}
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ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
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SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
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ib->ptr[ib->length_dw++] = lower_32_bits(pe);
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ib->ptr[ib->length_dw++] = upper_32_bits(pe);
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ib->ptr[ib->length_dw++] = ndw;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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ib->ptr[ib->length_dw++] = lower_32_bits(value);
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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value += incr;
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}
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}
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