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drm/i915: Move intel_vblank_evade() & co. into intel_vblank.c
intel_vblank.c seems like the appropriate place for the core vblank evasion code. Move it there. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231213102519.13500-8-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
This commit is contained in:
Ville Syrjälä
parent
318ec320c6
commit
dea1731dfc
3 changed files with 142 additions and 135 deletions
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@ -461,141 +461,6 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
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1000 * adjusted_mode->crtc_htotal);
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}
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static int intel_mode_vblank_start(const struct drm_display_mode *mode)
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{
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int vblank_start = mode->crtc_vblank_start;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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vblank_start = DIV_ROUND_UP(vblank_start, 2);
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return vblank_start;
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}
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struct intel_vblank_evade_ctx {
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struct intel_crtc *crtc;
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int min, max, vblank_start;
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bool need_vlv_dsi_wa;
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};
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static void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *new_crtc_state,
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struct intel_vblank_evade_ctx *evade)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state;
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const struct drm_display_mode *adjusted_mode;
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evade->crtc = crtc;
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evade->need_vlv_dsi_wa = (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) &&
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intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
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/*
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* During fastsets/etc. the transcoder is still
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* running with the old timings at this point.
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*
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* TODO: maybe just use the active timings here?
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*/
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if (intel_crtc_needs_modeset(new_crtc_state))
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crtc_state = new_crtc_state;
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else
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crtc_state = old_crtc_state;
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adjusted_mode = &crtc_state->hw.adjusted_mode;
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if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
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/* timing changes should happen with VRR disabled */
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drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
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new_crtc_state->update_m_n || new_crtc_state->update_lrr);
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if (intel_vrr_is_push_sent(crtc_state))
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evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
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else
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evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
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} else {
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evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
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}
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/* FIXME needs to be calibrated sensibly */
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evade->min = evade->vblank_start - intel_usecs_to_scanlines(adjusted_mode,
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VBLANK_EVASION_TIME_US);
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evade->max = evade->vblank_start - 1;
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/*
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* M/N and TRANS_VTOTAL are double buffered on the transcoder's
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* undelayed vblank, so with seamless M/N and LRR we must evade
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* both vblanks.
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*
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* DSB execution waits for the transcoder's undelayed vblank,
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* hence we must kick off the commit before that.
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*/
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if (new_crtc_state->dsb || new_crtc_state->update_m_n || new_crtc_state->update_lrr)
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evade->min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
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}
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/* must be called with vblank interrupt already enabled! */
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static int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
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{
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struct intel_crtc *crtc = evade->crtc;
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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long timeout = msecs_to_jiffies_timeout(1);
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wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
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DEFINE_WAIT(wait);
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int scanline;
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if (evade->min <= 0 || evade->max <= 0)
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return 0;
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for (;;) {
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/*
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* prepare_to_wait() has a memory barrier, which guarantees
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* other CPUs can see the task state update by the time we
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* read the scanline.
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*/
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prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
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scanline = intel_get_crtc_scanline(crtc);
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if (scanline < evade->min || scanline > evade->max)
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break;
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if (!timeout) {
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drm_err(&i915->drm,
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"Potential atomic update failure on pipe %c\n",
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pipe_name(crtc->pipe));
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break;
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}
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local_irq_enable();
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timeout = schedule_timeout(timeout);
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local_irq_disable();
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}
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finish_wait(wq, &wait);
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/*
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* On VLV/CHV DSI the scanline counter would appear to
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* increment approx. 1/3 of a scanline before start of vblank.
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* The registers still get latched at start of vblank however.
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* This means we must not write any registers on the first
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* line of vblank (since not the whole line is actually in
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* vblank). And unfortunately we can't use the interrupt to
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* wait here since it will fire too soon. We could use the
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* frame start interrupt instead since it will fire after the
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* critical scanline, but that would require more changes
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* in the interrupt code. So for now we'll just do the nasty
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* thing and poll for the bad scanline to pass us by.
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*
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* FIXME figure out if BXT+ DSI suffers from this as well
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*/
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while (evade->need_vlv_dsi_wa && scanline == evade->vblank_start)
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scanline = intel_get_crtc_scanline(crtc);
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return scanline;
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}
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/**
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* intel_pipe_update_start() - start update of a set of display registers
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* @state: the atomic state
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@ -5,6 +5,7 @@
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_crtc.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_vblank.h"
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@ -581,3 +582,132 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
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intel_vblank_section_exit(i915);
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spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags);
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}
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static int intel_mode_vblank_start(const struct drm_display_mode *mode)
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{
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int vblank_start = mode->crtc_vblank_start;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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vblank_start = DIV_ROUND_UP(vblank_start, 2);
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return vblank_start;
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}
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void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *new_crtc_state,
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struct intel_vblank_evade_ctx *evade)
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{
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struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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const struct intel_crtc_state *crtc_state;
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const struct drm_display_mode *adjusted_mode;
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evade->crtc = crtc;
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evade->need_vlv_dsi_wa = (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) &&
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intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
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/*
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* During fastsets/etc. the transcoder is still
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* running with the old timings at this point.
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*
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* TODO: maybe just use the active timings here?
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*/
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if (intel_crtc_needs_modeset(new_crtc_state))
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crtc_state = new_crtc_state;
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else
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crtc_state = old_crtc_state;
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adjusted_mode = &crtc_state->hw.adjusted_mode;
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if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
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/* timing changes should happen with VRR disabled */
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drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
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new_crtc_state->update_m_n || new_crtc_state->update_lrr);
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if (intel_vrr_is_push_sent(crtc_state))
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evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
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else
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evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
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} else {
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evade->vblank_start = intel_mode_vblank_start(adjusted_mode);
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}
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/* FIXME needs to be calibrated sensibly */
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evade->min = evade->vblank_start - intel_usecs_to_scanlines(adjusted_mode,
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VBLANK_EVASION_TIME_US);
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evade->max = evade->vblank_start - 1;
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/*
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* M/N and TRANS_VTOTAL are double buffered on the transcoder's
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* undelayed vblank, so with seamless M/N and LRR we must evade
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* both vblanks.
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*
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* DSB execution waits for the transcoder's undelayed vblank,
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* hence we must kick off the commit before that.
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*/
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if (new_crtc_state->dsb || new_crtc_state->update_m_n || new_crtc_state->update_lrr)
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evade->min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
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}
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/* must be called with vblank interrupt already enabled! */
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int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
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{
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struct intel_crtc *crtc = evade->crtc;
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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long timeout = msecs_to_jiffies_timeout(1);
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wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
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DEFINE_WAIT(wait);
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int scanline;
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if (evade->min <= 0 || evade->max <= 0)
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return 0;
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for (;;) {
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/*
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* prepare_to_wait() has a memory barrier, which guarantees
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* other CPUs can see the task state update by the time we
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* read the scanline.
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*/
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prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
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scanline = intel_get_crtc_scanline(crtc);
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if (scanline < evade->min || scanline > evade->max)
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break;
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if (!timeout) {
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drm_err(&i915->drm,
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"Potential atomic update failure on pipe %c\n",
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pipe_name(crtc->pipe));
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break;
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}
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local_irq_enable();
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timeout = schedule_timeout(timeout);
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local_irq_disable();
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}
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finish_wait(wq, &wait);
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/*
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* On VLV/CHV DSI the scanline counter would appear to
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* increment approx. 1/3 of a scanline before start of vblank.
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* The registers still get latched at start of vblank however.
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* This means we must not write any registers on the first
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* line of vblank (since not the whole line is actually in
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* vblank). And unfortunately we can't use the interrupt to
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* wait here since it will fire too soon. We could use the
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* frame start interrupt instead since it will fire after the
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* critical scanline, but that would require more changes
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* in the interrupt code. So for now we'll just do the nasty
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* thing and poll for the bad scanline to pass us by.
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*
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* FIXME figure out if BXT+ DSI suffers from this as well
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*/
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while (evade->need_vlv_dsi_wa && scanline == evade->vblank_start)
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scanline = intel_get_crtc_scanline(crtc);
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return scanline;
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}
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@ -13,6 +13,18 @@ struct drm_crtc;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_vblank_evade_ctx {
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struct intel_crtc *crtc;
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int min, max, vblank_start;
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bool need_vlv_dsi_wa;
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};
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void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
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const struct intel_crtc_state *new_crtc_state,
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struct intel_vblank_evade_ctx *evade);
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/* must be called with vblank interrupt already enabled! */
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int intel_vblank_evade(struct intel_vblank_evade_ctx *evade);
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u32 i915_get_vblank_counter(struct drm_crtc *crtc);
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u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
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bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
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