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drm/amd/amdgpu: Port MMHUB over to new SOC15 macros
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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parent
805cb75ccb
commit
deca8322f1
1 changed files with 11 additions and 14 deletions
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@ -200,8 +200,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
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uint32_t tmp;
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for (i = 0; i <= 14; i++) {
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tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)
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+ i);
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tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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ENABLE_CONTEXT, 1);
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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@ -223,12 +222,12 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
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tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
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PAGE_TABLE_BLOCK_SIZE,
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adev->vm_manager.block_size - 9);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL) + i, tmp);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2,
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WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
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lower_32_bits(adev->vm_manager.max_pfn - 1));
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WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
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WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
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upper_32_bits(adev->vm_manager.max_pfn - 1));
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}
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}
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@ -238,12 +237,10 @@ static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
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unsigned i;
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for (i = 0; i < 18; ++i) {
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) +
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2 * i, 0xffffffff);
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WREG32(SOC15_REG_OFFSET(MMHUB, 0,
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mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) +
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2 * i, 0x1f);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
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2 * i, 0xffffffff);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
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2 * i, 0x1f);
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}
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}
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@ -282,7 +279,7 @@ void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
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/* Disable all tables */
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for (i = 0; i < 16; i++)
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WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL) + i, 0);
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WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
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/* Setup TLB control */
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tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
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