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arm64: dts: bitmain: Source common clock for UART controllers
Remove fixed clock and source common clock for UART controllers. Link: https://lore.kernel.org/r/20200114040311.6599-3-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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parent
e1cd7b8046
commit
dee0be5c21
2 changed files with 12 additions and 9 deletions
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@ -49,12 +49,6 @@ memory@0 {
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reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
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};
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uart_clk: uart-clk {
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compatible = "fixed-clock";
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clock-frequency = <500000000>;
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#clock-cells = <0>;
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};
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soc {
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gpio0: gpio@50027000 {
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porta: gpio-controller@0 {
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@ -173,21 +167,18 @@ pinmux {
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&uart0 {
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status = "okay";
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clocks = <&uart_clk>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0_default>;
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};
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&uart1 {
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status = "okay";
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clocks = <&uart_clk>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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&uart2 {
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status = "okay";
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clocks = <&uart_clk>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_default>;
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};
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@ -174,6 +174,9 @@ portc: gpio-controller@0 {
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uart0: serial@58018000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x58018000 0x0 0x2000>;
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clocks = <&clk BM1880_CLK_UART_500M>,
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<&clk BM1880_CLK_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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@ -184,6 +187,9 @@ uart0: serial@58018000 {
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uart1: serial@5801A000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801a000 0x0 0x2000>;
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clocks = <&clk BM1880_CLK_UART_500M>,
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<&clk BM1880_CLK_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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@ -194,6 +200,9 @@ uart1: serial@5801A000 {
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uart2: serial@5801C000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801c000 0x0 0x2000>;
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clocks = <&clk BM1880_CLK_UART_500M>,
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<&clk BM1880_CLK_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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@ -204,6 +213,9 @@ uart2: serial@5801C000 {
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uart3: serial@5801E000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801e000 0x0 0x2000>;
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clocks = <&clk BM1880_CLK_UART_500M>,
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<&clk BM1880_CLK_APB_UART>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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